[U-Boot] [PATCH v3 07/10] pinctrl: rockchip: Split the common set_pull() func into per Soc【请注意，邮件由u-boot-bounces at lists.denx.de代发】
Kever Yang
kever.yang at rock-chips.com
Thu May 9 01:26:13 UTC 2019
On 05/07/2019 11:43 AM, Kever Yang wrote:
>
> On 04/16/2019 09:57 PM, David Wu wrote:
>> As the common set_mux func(), implement the feature at the own file
>> for each Soc.
>>
>> Signed-off-by: David Wu <david.wu at rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang at rock-chips.com>
Applied to u-boot-rockchip, thanks!
>
> Thanks,
> - Kever
>> ---
>>
>> Change in v3:
>> - None
>>
>> drivers/pinctrl/rockchip/pinctrl-rk3036.c | 23 ++++-
>> drivers/pinctrl/rockchip/pinctrl-rk3128.c | 23 ++++-
>> drivers/pinctrl/rockchip/pinctrl-rk3188.c | 29 +++++-
>> drivers/pinctrl/rockchip/pinctrl-rk322x.c | 29 +++++-
>> drivers/pinctrl/rockchip/pinctrl-rk3288.c | 40 ++++++--
>> drivers/pinctrl/rockchip/pinctrl-rk3328.c | 29 +++++-
>> drivers/pinctrl/rockchip/pinctrl-rk3368.c | 40 ++++++--
>> drivers/pinctrl/rockchip/pinctrl-rk3399.c | 40 ++++++--
>> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 97 ++++---------------
>> drivers/pinctrl/rockchip/pinctrl-rockchip.h | 7 +-
>> drivers/pinctrl/rockchip/pinctrl-rv1108.c | 30 +++++-
>> 11 files changed, 275 insertions(+), 112 deletions(-)
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> index 8969aea2e3..498b633f22 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> @@ -53,6 +53,27 @@ static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> *bit = pin_num % RK3036_PULL_PINS_PER_REG;
>> };
>>
>> +static int rk3036_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit;
>> + u32 data;
>> +
>> + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
>> + pull != PIN_CONFIG_BIAS_DISABLE)
>> + return -ENOTSUPP;
>> +
>> + rk3036_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
>> + data = BIT(bit + 16);
>> + if (pull == PIN_CONFIG_BIAS_DISABLE)
>> + data |= BIT(bit);
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> static struct rockchip_pin_bank rk3036_pin_banks[] = {
>> PIN_BANK(0, 32, "gpio0"),
>> PIN_BANK(1, 32, "gpio1"),
>> @@ -66,7 +87,7 @@ static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
>> .type = RK3036,
>> .grf_mux_offset = 0xa8,
>> .set_mux = rk3036_set_mux,
>> - .pull_calc_reg = rk3036_calc_pull_reg_and_bit,
>> + .set_pull = rk3036_set_pull,
>> };
>>
>> static const struct udevice_id rk3036_pinctrl_ids[] = {
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> index de203334c7..104b76c19e 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> @@ -152,6 +152,27 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> *bit = pin_num % RK3128_PULL_PINS_PER_REG;
>> }
>>
>> +static int rk3128_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit;
>> + u32 data;
>> +
>> + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
>> + pull != PIN_CONFIG_BIAS_DISABLE)
>> + return -ENOTSUPP;
>> +
>> + rk3128_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
>> + data = BIT(bit + 16);
>> + if (pull == PIN_CONFIG_BIAS_DISABLE)
>> + data |= BIT(bit);
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> static struct rockchip_pin_bank rk3128_pin_banks[] = {
>> PIN_BANK(0, 32, "gpio0"),
>> PIN_BANK(1, 32, "gpio1"),
>> @@ -170,7 +191,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
>> .iomux_routes = rk3128_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
>> .set_mux = rk3128_set_mux,
>> - .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
>> + .set_pull = rk3128_set_pull,
>> };
>>
>> static const struct udevice_id rk3128_pinctrl_ids[] = {
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c
>> index 617ae28ac8..e09c799e72 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c
>> @@ -71,6 +71,33 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> }
>> }
>>
>> +static int rk3188_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit, type;
>> + u32 data;
>> +
>> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
>> + return -ENOTSUPP;
>> +
>> + rk3188_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
>> + type = bank->pull_type[pin_num / 8];
>> + ret = rockchip_translate_pull_value(type, pull);
>> + if (ret < 0) {
>> + debug("unsupported pull setting %d\n", pull);
>> + return ret;
>> + }
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
>> + data |= (ret << bit);
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> static struct rockchip_pin_bank rk3188_pin_banks[] = {
>> PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
>> PIN_BANK(1, 32, "gpio1"),
>> @@ -85,7 +112,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
>> .type = RK3188,
>> .grf_mux_offset = 0x60,
>> .set_mux = rk3188_set_mux,
>> - .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
>> + .set_pull = rk3188_set_pull,
>> };
>>
>> static const struct udevice_id rk3188_pinctrl_ids[] = {
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
>> index 10200ff3c8..b69d9795bb 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
>> @@ -191,6 +191,33 @@ static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> }
>>
>> +static int rk3228_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit, type;
>> + u32 data;
>> +
>> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
>> + return -ENOTSUPP;
>> +
>> + rk3228_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
>> + type = bank->pull_type[pin_num / 8];
>> + ret = rockchip_translate_pull_value(type, pull);
>> + if (ret < 0) {
>> + debug("unsupported pull setting %d\n", pull);
>> + return ret;
>> + }
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
>> + data |= (ret << bit);
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3228_DRV_GRF_OFFSET 0x200
>>
>> static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>> @@ -247,7 +274,7 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
>> .iomux_routes = rk3228_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
>> .set_mux = rk3228_set_mux,
>> - .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
>> + .set_pull = rk3228_set_pull,
>> .set_drive = rk3228_set_drive,
>> };
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
>> index d1b9aeb3d9..9192aa3949 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
>> @@ -82,10 +82,6 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> if (bank->bank_num == 0) {
>> *regmap = priv->regmap_pmu;
>> *reg = RK3288_PULL_PMU_OFFSET;
>> -
>> - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
>> - *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
>> - *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> } else {
>> *regmap = priv->regmap_base;
>> *reg = RK3288_PULL_OFFSET;
>> @@ -93,11 +89,39 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> /* correct the offset, as we're starting with the 2nd bank */
>> *reg -= 0x10;
>> *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
>> - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
>> + }
>> +
>> + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
>> + *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> +}
>> +
>> +static int rk3288_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit, type;
>> + u32 data;
>> +
>> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
>> + return -ENOTSUPP;
>>
>> - *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
>> - *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> + rk3288_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
>> + type = bank->pull_type[pin_num / 8];
>> + ret = rockchip_translate_pull_value(type, pull);
>> + if (ret < 0) {
>> + debug("unsupported pull setting %d\n", pull);
>> + return ret;
>> }
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
>> + data |= (ret << bit);
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> }
>>
>> #define RK3288_DRV_PMU_OFFSET 0x70
>> @@ -199,7 +223,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
>> .iomux_routes = rk3288_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
>> .set_mux = rk3288_set_mux,
>> - .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
>> + .set_pull = rk3288_set_pull,
>> .set_drive = rk3288_set_drive,
>> };
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
>> index 0ad5669d26..7ac5c0226e 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
>> @@ -174,6 +174,33 @@ static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> }
>>
>> +static int rk3328_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit, type;
>> + u32 data;
>> +
>> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
>> + return -ENOTSUPP;
>> +
>> + rk3328_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
>> + type = bank->pull_type[pin_num / 8];
>> + ret = rockchip_translate_pull_value(type, pull);
>> + if (ret < 0) {
>> + debug("unsupported pull setting %d\n", pull);
>> + return ret;
>> + }
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
>> + data |= (ret << bit);
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3328_DRV_GRF_OFFSET 0x200
>>
>> static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>> @@ -262,7 +289,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
>> .iomux_routes = rk3328_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
>> .set_mux = rk3328_set_mux,
>> - .pull_calc_reg = rk3328_calc_pull_reg_and_bit,
>> + .set_pull = rk3328_set_pull,
>> .set_drive = rk3328_set_drive,
>> .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
>> };
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
>> index 40cc846fa8..06de27aa30 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
>> @@ -48,10 +48,6 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> if (bank->bank_num == 0) {
>> *regmap = priv->regmap_pmu;
>> *reg = RK3368_PULL_PMU_OFFSET;
>> -
>> - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
>> - *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
>> - *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> } else {
>> *regmap = priv->regmap_base;
>> *reg = RK3368_PULL_GRF_OFFSET;
>> @@ -59,11 +55,39 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> /* correct the offset, as we're starting with the 2nd bank */
>> *reg -= 0x10;
>> *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
>> - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
>> + }
>> +
>> + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
>> + *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> +}
>> +
>> +static int rk3368_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit, type;
>> + u32 data;
>>
>> - *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
>> - *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
>> + return -ENOTSUPP;
>> +
>> + rk3368_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
>> + type = bank->pull_type[pin_num / 8];
>> + ret = rockchip_translate_pull_value(type, pull);
>> + if (ret < 0) {
>> + debug("unsupported pull setting %d\n", pull);
>> + return ret;
>> }
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
>> + data |= (ret << bit);
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> }
>>
>> #define RK3368_DRV_PMU_OFFSET 0x20
>> @@ -136,7 +160,7 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
>> .grf_mux_offset = 0x0,
>> .pmu_mux_offset = 0x0,
>> .set_mux = rk3368_set_mux,
>> - .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
>> + .set_pull = rk3368_set_pull,
>> .set_drive = rk3368_set_drive,
>> };
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c
>> index 82c8feeb7b..68bb492a6b 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c
>> @@ -98,10 +98,6 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> *reg = RK3399_PULL_PMU_OFFSET;
>>
>> *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
>> -
>> - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
>> - *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
>> - *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> } else {
>> *regmap = priv->regmap_base;
>> *reg = RK3399_PULL_GRF_OFFSET;
>> @@ -109,11 +105,39 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> /* correct the offset, as we're starting with the 3rd bank */
>> *reg -= 0x20;
>> *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
>> - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
>> + }
>> +
>> + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
>> + *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> +}
>> +
>> +static int rk3399_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit, type;
>> + u32 data;
>>
>> - *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
>> - *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
>> + return -ENOTSUPP;
>> +
>> + rk3399_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
>> + type = bank->pull_type[pin_num / 8];
>> + ret = rockchip_translate_pull_value(type, pull);
>> + if (ret < 0) {
>> + debug("unsupported pull setting %d\n", pull);
>> + return ret;
>> }
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
>> + data |= (ret << bit);
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> }
>>
>> static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>> @@ -275,7 +299,7 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
>> .iomux_routes = rk3399_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
>> .set_mux = rk3399_set_mux,
>> - .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
>> + .set_pull = rk3399_set_pull,
>> .set_drive = rk3399_set_drive,
>> };
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
>> index 439e8ba1b5..b3379a0d3f 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
>> @@ -270,61 +270,35 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
>> },
>> };
>>
>> +int rockchip_translate_pull_value(int type, int pull)
>> +{
>> + int i, ret;
>> +
>> + ret = -EINVAL;
>> + for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
>> + i++) {
>> + if (rockchip_pull_list[type][i] == pull) {
>> + ret = i;
>> + break;
>> + }
>> + }
>> +
>> + return ret;
>> +}
>> +
>> static int rockchip_set_pull(struct rockchip_pin_bank *bank,
>> int pin_num, int pull)
>> {
>> struct rockchip_pinctrl_priv *priv = bank->priv;
>> struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> - struct regmap *regmap;
>> - int reg, ret, i, pull_type;
>> - u8 bit;
>> - u32 data;
>>
>> debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
>> pin_num, pull);
>>
>> - ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
>> -
>> - switch (ctrl->type) {
>> - case RK3036:
>> - case RK3128:
>> - data = BIT(bit + 16);
>> - if (pull == PIN_CONFIG_BIAS_DISABLE)
>> - data |= BIT(bit);
>> - ret = regmap_write(regmap, reg, data);
>> - break;
>> - case RV1108:
>> - case RK3188:
>> - case RK3288:
>> - case RK3368:
>> - case RK3399:
>> - pull_type = bank->pull_type[pin_num / 8];
>> - ret = -EINVAL;
>> - for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
>> - i++) {
>> - if (rockchip_pull_list[pull_type][i] == pull) {
>> - ret = i;
>> - break;
>> - }
>> - }
>> -
>> - if (ret < 0) {
>> - debug("unsupported pull setting %d\n", pull);
>> - return ret;
>> - }
>> -
>> - /* enable the write to the equivalent lower bits */
>> - data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
>> - data |= (ret << bit);
>> -
>> - ret = regmap_write(regmap, reg, data);
>> - break;
>> - default:
>> - debug("unsupported pinctrl type\n");
>> - return -EINVAL;
>> - }
>> + if (!ctrl->set_pull)
>> + return -ENOTSUPP;
>>
>> - return ret;
>> + return ctrl->set_pull(bank, pin_num, pull);
>> }
>>
>> static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
>> @@ -350,28 +324,6 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
>> return regmap_write(regmap, reg, data);
>> }
>>
>> -/*
>> - * Pinconf_ops handling
>> - */
>> -static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
>> - unsigned int pull)
>> -{
>> - switch (ctrl->type) {
>> - case RK3036:
>> - case RK3128:
>> - return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
>> - pull == PIN_CONFIG_BIAS_DISABLE);
>> - case RV1108:
>> - case RK3188:
>> - case RK3288:
>> - case RK3368:
>> - case RK3399:
>> - return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
>> - }
>> -
>> - return false;
>> -}
>> -
>> /* set the pin config settings for a specified pin */
>> static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
>> u32 pin, u32 param, u32 arg)
>> @@ -382,21 +334,10 @@ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
>>
>> switch (param) {
>> case PIN_CONFIG_BIAS_DISABLE:
>> - rc = rockchip_set_pull(bank, pin, param);
>> - if (rc)
>> - return rc;
>> - break;
>> -
>> case PIN_CONFIG_BIAS_PULL_UP:
>> case PIN_CONFIG_BIAS_PULL_DOWN:
>> case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
>> case PIN_CONFIG_BIAS_BUS_HOLD:
>> - if (!rockchip_pinconf_pull_valid(ctrl, param))
>> - return -ENOTSUPP;
>> -
>> - if (!arg)
>> - return -EINVAL;
>> -
>> rc = rockchip_set_pull(bank, pin, param);
>> if (rc)
>> return rc;
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
>> index 2ef24dce6c..c21b79602c 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
>> @@ -279,10 +279,8 @@ struct rockchip_pin_ctrl {
>>
>> int (*set_mux)(struct rockchip_pin_bank *bank,
>> int pin, int mux);
>> -
>> - void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
>> - int pin_num, struct regmap **regmap,
>> - int *reg, u8 *bit);
>> + int (*set_pull)(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull);
>> int (*set_drive)(struct rockchip_pin_bank *bank,
>> int pin_num, int strength);
>> int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
>> @@ -306,5 +304,6 @@ bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
>> int mux, u32 *reg, u32 *value);
>> int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask);
>> int rockchip_translate_drive_value(int type, int strength);
>> +int rockchip_translate_pull_value(int type, int pull);
>>
>> #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c
>> index 1a150ff0f1..6456483e36 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c
>> @@ -128,6 +128,34 @@ static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
>> }
>>
>> +static int rv1108_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit, type;
>> + u32 data;
>> +
>> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
>> + return -ENOTSUPP;
>> +
>> + rv1108_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
>> + type = bank->pull_type[pin_num / 8];
>> + ret = rockchip_translate_pull_value(type, pull);
>> + if (ret < 0) {
>> + debug("unsupported pull setting %d\n", pull);
>> + return ret;
>> + }
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
>> +
>> + data |= (ret << bit);
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RV1108_DRV_PMU_OFFSET 0x20
>> #define RV1108_DRV_GRF_OFFSET 0x210
>>
>> @@ -229,7 +257,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
>> .iomux_recalced = rv1108_mux_recalced_data,
>> .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
>> .set_mux = rv1108_set_mux,
>> - .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
>> + .set_pull = rv1108_set_pull,
>> .set_drive = rv1108_set_drive,
>> .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
>> };
>
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