[U-Boot] [PATCH] armv8: ls1046afrwy: Add support for LS1046AFRWY platform
Vabhav Sharma
vabhav.sharma at nxp.com
Thu May 9 14:03:37 UTC 2019
LS1046AFRWY board supports LS1046A family SoCs. This patch
add base support for this board.
Board support's 4GB ddr memory, i2c, micro-click module,microSD card,
serial console,qspi nor flash,ifc nand flash,qsgmii network interface,
usb 3.0 and serdes interface to support two x1gen3 pcie interface.
Signed-off-by: Camelia Groza <camelia.groza at nxp.com>
Signed-off-by: Madalin Bucur <madalin.bucur at nxp.com>
Signed-off-by: Pankit Garg <pankit.garg at nxp.com>
Signed-off-by: Pramod Kumar <pramod.kumar_1 at nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma at nxp.com>
---
arch/arm/Kconfig | 17 ++
arch/arm/cpu/armv8/Kconfig | 1 +
arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 2 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-ls1046a-frwy.dts | 34 +++
board/freescale/ls1046afrwy/Kconfig | 17 ++
board/freescale/ls1046afrwy/MAINTAINERS | 17 ++
board/freescale/ls1046afrwy/Makefile | 9 +
board/freescale/ls1046afrwy/README | 76 +++++++
board/freescale/ls1046afrwy/ddr.c | 24 ++
board/freescale/ls1046afrwy/eth.c | 114 ++++++++++
board/freescale/ls1046afrwy/ls1046afrwy.c | 249 +++++++++++++++++++++
board/freescale/ls1046afrwy/ls1046afrwy_pbi.cfg | 22 ++
.../freescale/ls1046afrwy/ls1046afrwy_qspi_pbi.cfg | 26 +++
.../freescale/ls1046afrwy/ls1046afrwy_rcw_qspi.cfg | 7 +
board/freescale/ls1046afrwy/ls1046afrwy_rcw_sd.cfg | 7 +
configs/ls1046afrwy_tfa_defconfig | 58 +++++
include/configs/ls1046a_common.h | 13 +-
include/configs/ls1046afrwy.h | 204 +++++++++++++++++
include/fm_eth.h | 12 +
20 files changed, 908 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/fsl-ls1046a-frwy.dts
create mode 100644 board/freescale/ls1046afrwy/Kconfig
create mode 100644 board/freescale/ls1046afrwy/MAINTAINERS
create mode 100644 board/freescale/ls1046afrwy/Makefile
create mode 100644 board/freescale/ls1046afrwy/README
create mode 100644 board/freescale/ls1046afrwy/ddr.c
create mode 100644 board/freescale/ls1046afrwy/eth.c
create mode 100644 board/freescale/ls1046afrwy/ls1046afrwy.c
create mode 100644 board/freescale/ls1046afrwy/ls1046afrwy_pbi.cfg
create mode 100644 board/freescale/ls1046afrwy/ls1046afrwy_qspi_pbi.cfg
create mode 100644 board/freescale/ls1046afrwy/ls1046afrwy_rcw_qspi.cfg
create mode 100644 board/freescale/ls1046afrwy/ls1046afrwy_rcw_sd.cfg
create mode 100644 configs/ls1046afrwy_tfa_defconfig
create mode 100644 include/configs/ls1046afrwy.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f91c590..15699a2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1329,6 +1329,22 @@ config TARGET_LS1046ARDB
development platform that supports the QorIQ LS1046A
Layerscape Architecture processor.
+config TARGET_LS1046AFRWY
+ bool "Support ls1046afrwy"
+ select ARCH_LS1046A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select DM_SPI_FLASH if DM_SPI
+ select POWER_MC34VR500
+ select SUPPORT_SPL
+ imply SCSI
+ help
+ Support for Freescale LS1046AFRWY platform.
+ The LS1046A Freeway Board (FRWY) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -1617,6 +1633,7 @@ source "board/freescale/ls1021aiot/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/ls1046ardb/Kconfig"
+source "board/freescale/ls1046afrwy/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 7405c3a..ed31df1 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -106,6 +106,7 @@ config PSCI_RESET
!TARGET_LS1012AFRWY && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
+ !TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
!TARGET_LX2160AQDS && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
index f8310f2..caa4862 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*/
#include <common.h>
@@ -33,6 +34,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
SGMII_FM1_DTSEC6} },
{0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x3040, {NONE, NONE, QSGMII_FM1_A, NONE} },
{}
};
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8b97143..4c53662 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -316,6 +316,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1046a-qds-duart.dtb \
fsl-ls1046a-qds-lpuart.dtb \
fsl-ls1046a-rdb.dtb \
+ fsl-ls1046a-frwy.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-2g5rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts
new file mode 100644
index 0000000..3d41e3b
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-frwy.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Device Tree Include file for NXP Layerscape-1046A family SoC.
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1046a.dtsi"
+
+/ {
+ model = "LS1046A FRWY Board";
+
+ aliases {
+ spi0 = &qspi;
+ };
+
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: mt25qu512abb8esf at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+
+};
+
diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig
new file mode 100644
index 0000000..6a4c3e9
--- /dev/null
+++ b/board/freescale/ls1046afrwy/Kconfig
@@ -0,0 +1,17 @@
+
+if TARGET_LS1046AFRWY
+
+config SYS_BOARD
+ default "ls1046afrwy"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1046afrwy"
+
+source "board/freescale/common/Kconfig"
+endif
diff --git a/board/freescale/ls1046afrwy/MAINTAINERS b/board/freescale/ls1046afrwy/MAINTAINERS
new file mode 100644
index 0000000..9ee9de3
--- /dev/null
+++ b/board/freescale/ls1046afrwy/MAINTAINERS
@@ -0,0 +1,17 @@
+LS1046AFRWY BOARD
+M: Pramod Kumar <pramod.kumar_1 at nxp.com>
+S: Maintained
+F: board/freescale/ls1046afrwy/
+F: board/freescale/ls1046afrwy/ls1046afrwy.c
+F: include/configs/ls1046afrwy.h
+F: configs/ls1046afrwy_qspi_defconfig
+F: configs/ls1046afrwy_qspi_spl_defconfig
+F: configs/ls1046afrwy_sdcard_defconfig
+F: configs/ls1046afrwy_tfa_defconfig
+
+LS1046A_SECURE_BOOT BOARD
+M: Ruchika Gupta <ruchika.gupta at nxp.com>
+S: Maintained
+F: configs/ls1046afrwy_SECURE_BOOT_defconfig
+F: configs/ls1046afrwy_sdcard_SECURE_BOOT_defconfig
+F: configs/ls1046afrwy_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1046afrwy/Makefile b/board/freescale/ls1046afrwy/Makefile
new file mode 100644
index 0000000..88089e6
--- /dev/null
+++ b/board/freescale/ls1046afrwy/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 NXP
+
+obj-y += ddr.o
+obj-y += ls1046afrwy.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_NET) += eth.o
+endif
diff --git a/board/freescale/ls1046afrwy/README b/board/freescale/ls1046afrwy/README
new file mode 100644
index 0000000..d7b5a77
--- /dev/null
+++ b/board/freescale/ls1046afrwy/README
@@ -0,0 +1,76 @@
+Overview
+--------
+The LS1046A Freeway Board (iFRWY) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1046A
+LayerScape Architecture processor. The FRWY-LS1046A provides SW development
+platform for the Freescale LS1046A processor series, with a complete
+debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant.
+
+LS1046A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
+SoC overview.
+
+ FRWY-LS1046A board Overview
+ -----------------------
+ - SERDES1 Connections, 4 lanes supporting:
+ - Lane0: Unused
+ - Lane1: Unused
+ - Lane2: QSGMII
+ - Lane3: Unused
+ - SERDES2 Connections, 4 lanes supporting:
+ - Lane0: Unused
+ - Lane1: PCIe3 with PCIe x1 slot
+ - Lane2: Unused
+ - Lane3: PCIe3 with PCIe x1 slot
+ - DDR Controller
+ - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
+ -IFC/Local Bus
+ - One 512 MB NAND flash with ECC support
+ - USB 3.0
+ - Two Type A port
+ - SDHC: connects directly to a full microSD slot
+ - QSPI: 64 MB high-speed flash Memory for boot code and storage
+ - 4 I2C controllers
+ - UART
+ - Two 4-pin serial ports at up to 115.2 Kbit/s
+ - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address End Address Description Size
+0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
+0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
+0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
+0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
+0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
+0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
+0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
+0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
+0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
+0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
+0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
+0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
+
+QSPI flash map:
+Start Address End Address Description Size
+0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB
+0x00_4010_0000 - 0x00_404F_FFFF FIP Image
+ (Bl31 + BL32(optee.
+ bin) + Bl33(uboot)
+ + headers for secure
+ boot) 4MB
+0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB
+0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB
+0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
+0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
+0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB
+0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
+
+Booting Options
+---------------
+a) QSPI boot
+b) microSD boot
diff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c
new file mode 100644
index 0000000..9f4e1a8
--- /dev/null
+++ b/board/freescale/ls1046afrwy/ddr.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c
new file mode 100644
index 0000000..9f8bd92
--- /dev/null
+++ b/board/freescale/ls1046afrwy/eth.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_dtsec.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct memac_mdio_info dtsec_mdio_info;
+ struct mii_dev *dev;
+ u32 srds_s1;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ /* QSGMII on lane B, MAC 6/5/10/1 */
+ fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
+
+ switch (srds_s1) {
+ case 0x3040:
+ break;
+ default:
+ printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
+ srds_s1);
+ break;
+ }
+
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(FM1_DTSEC6, dev);
+ fm_info_set_mdio(FM1_DTSEC5, dev);
+ fm_info_set_mdio(FM1_DTSEC10, dev);
+ fm_info_set_mdio(FM1_DTSEC1, dev);
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_FMAN_ENET
+int fdt_update_ethernet_dt(void *blob)
+{
+ u32 srds_s1;
+ int i, prop;
+ int offset, nodeoff;
+ const char *path;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ /* Cycle through all aliases */
+ for (prop = 0; ; prop++) {
+ const char *name;
+
+ /* FDT might have been edited, recompute the offset */
+ offset = fdt_first_property_offset(blob,
+ fdt_path_offset(blob,
+ "/aliases")
+ );
+ /* Select property number 'prop' */
+ for (i = 0; i < prop; i++)
+ offset = fdt_next_property_offset(blob, offset);
+
+ if (offset < 0)
+ break;
+
+ path = fdt_getprop_by_offset(blob, offset, &name, NULL);
+ nodeoff = fdt_path_offset(blob, path);
+
+ switch (srds_s1) {
+ case 0x3040:
+ if (!strcmp(name, "ethernet1"))
+ fdt_status_disabled(blob, nodeoff);
+ if (!strcmp(name, "ethernet2"))
+ fdt_status_disabled(blob, nodeoff);
+ if (!strcmp(name, "ethernet3"))
+ fdt_status_disabled(blob, nodeoff);
+ if (!strcmp(name, "ethernet6"))
+ fdt_status_disabled(blob, nodeoff);
+ break;
+ default:
+ printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n",
+ __func__, srds_s1);
+ break;
+ }
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
new file mode 100644
index 0000000..8539fa2
--- /dev/null
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <power/mc34vr500_pmic.h>
+#include <fsl_sec.h>
+#include <fsl_dspi.h>
+
+#define LS1046A_PORSR1_REG 0x1EE0000
+#define BOOT_SRC_SD 0x20000000
+#define BOOT_SRC_MASK 0xFF800000
+#define BOARD_REV_GPIO 13
+#define USB2_SEL_MASK 0x00000100
+
+#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
+(((word) & 0x00ff0000) >> 8) | \
+(((word) & 0x0000ff00) << 8) | \
+(((word) & 0x000000ff) << 24))
+#define SPI_MCR_REG 0x2100000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static inline void demux_select_usb2(void)
+{
+ u32 val;
+ struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
+
+ val = in_be32(&pgpio->gpdir);
+ val |= USB2_SEL_MASK;
+ out_be32(&pgpio->gpdir, val);
+
+ val = in_be32(&pgpio->gpdat);
+ val |= USB2_SEL_MASK;
+ out_be32(&pgpio->gpdat, val);
+}
+
+static inline void set_spi_cs_signal_inactive(void)
+{
+ /* default: all CS signals inactive state is high */
+ uint mcr_val;
+ uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
+ DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+
+ mcr_val = in_be32(SPI_MCR_REG);
+ mcr_val |= DSPI_MCR_HALT;
+ out_be32(SPI_MCR_REG, mcr_val);
+ out_be32(SPI_MCR_REG, mcr_cfg_val);
+ mcr_val = in_be32(SPI_MCR_REG);
+ mcr_val &= ~DSPI_MCR_HALT;
+ out_be32(SPI_MCR_REG, mcr_val);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static inline uint8_t get_board_version(void)
+{
+ u8 val;
+ struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
+
+ val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03;
+
+ return val;
+}
+
+int checkboard(void)
+{
+ static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
+ u32 boot_src;
+ u8 rev;
+
+ rev = get_board_version();
+ switch (rev) {
+ case 0x00:
+ puts("Board: LS1046AFRWY, Rev: A, boot from ");
+ break;
+ case 0x01:
+ puts("Board: LS1046AFRWY, Rev: B, boot from ");
+ break;
+ default:
+ puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
+ break;
+ }
+ boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
+
+ if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
+ puts("SD\n");
+ else
+ puts("QSPI\n");
+ printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
+
+ return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_SECURE_BOOT
+ /*
+ * In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ u32 val;
+val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
+
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ return 0;
+}
+
+int board_setup_core_volt(u32 vdd)
+{
+ return 0;
+}
+
+int get_serdes_volt(void)
+{
+ return mc34vr500_get_sw_volt(SW4);
+}
+
+int set_serdes_volt(int svdd)
+{
+ return mc34vr500_set_sw_volt(SW4, svdd);
+}
+
+int power_init_board(void)
+{
+ int ret;
+
+ ret = power_mc34vr500_init(0);
+ if (ret)
+ return ret;
+
+ setup_chip_volt();
+
+ return 0;
+}
+
+void config_board_mux(void)
+{
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 usb_pwrfault;
+ /*
+ * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
+ * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+ */
+ out_be32(&scfg->rcwpmuxcr0, 0x3300);
+#ifdef CONFIG_HAS_FSL_IIC3
+ /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
+ out_be32(&scfg->rcwpmuxcr0, 0x0000);
+#endif
+ out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+ usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED <<
+ SCFG_USBPWRFAULT_USB1_SHIFT);
+ out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#ifndef CONFIG_HAS_FSL_IIC3
+ /*
+ * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
+ * to select I2C3_USB2_SEL_IO
+ * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
+ * I2C3 header (default)
+ * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
+ * USB2 port
+ * programmed to select USB2 by setting GPIO3_23 output to one
+ */
+ demux_select_usb2();
+#endif
+#endif
+ set_spi_cs_signal_inactive();
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ config_board_mux();
+ return 0;
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ /* fixup DT for the two DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+#endif
+
+ fdt_fixup_icid(blob);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy_pbi.cfg b/board/freescale/ls1046afrwy/ls1046afrwy_pbi.cfg
new file mode 100644
index 0000000..5478217
--- /dev/null
+++ b/board/freescale/ls1046afrwy/ls1046afrwy_pbi.cfg
@@ -0,0 +1,22 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#Serdes SATA
+09eb1300 80104e20
+09eb08dc 00502880
+#PEX gen3 link
+09570158 00000300
+89400890 01048000
+89500890 01048000
+89600890 01048000
+#Alt base register
+09570158 00001000
+#flush PBI data
+096100c0 000fffff
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy_qspi_pbi.cfg b/board/freescale/ls1046afrwy/ls1046afrwy_qspi_pbi.cfg
new file mode 100644
index 0000000..735d46c
--- /dev/null
+++ b/board/freescale/ls1046afrwy/ls1046afrwy_qspi_pbi.cfg
@@ -0,0 +1,26 @@
+#QSPI clk
+0957015c 40100000
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#Serdes SATA
+09eb1300 80104e20
+09eb08dc 00502880
+#PEX gen3 link
+09570158 00000300
+89400890 01048000
+89500890 01048000
+89600890 01048000
+#Alt base register
+09570158 00001000
+#flush PBI data
+096100c0 000fffff
+#Change endianness
+09550000 000f400c
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy_rcw_qspi.cfg b/board/freescale/ls1046afrwy/ls1046afrwy_rcw_qspi.cfg
new file mode 100644
index 0000000..7b9be0a
--- /dev/null
+++ b/board/freescale/ls1046afrwy/ls1046afrwy_rcw_qspi.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0c150010 0e000000 00000000 00000000
+11335559 40005012 40025000 c1000000
+00000000 00000000 00000000 00238800
+20124000 00003101 00000096 00000001
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy_rcw_sd.cfg b/board/freescale/ls1046afrwy/ls1046afrwy_rcw_sd.cfg
new file mode 100644
index 0000000..d3b1522
--- /dev/null
+++ b/board/freescale/ls1046afrwy/ls1046afrwy_rcw_sd.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0c150012 0e000000 00000000 00000000
+11335559 40005012 60040000 c1000000
+00000000 00000000 00000000 00238800
+20124000 00003101 00000096 00000001
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
new file mode 100644
index 0000000..1e83c5f
--- /dev/null
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AFRWY=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY_VITESSE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index ea6209a..757ccc4 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor
+ * Copyright 2019 NXP
*/
#ifndef __LS1046A_COMMON_H
@@ -206,6 +207,15 @@
#include <config_distro_bootcmd.h>
#endif
+#if defined(CONFIG_TARGET_LS1046AFRWY)
+#define LS1046A_BOOT_SRC_AND_HDR\
+ "boot_scripts=ls1046afrwy_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
+#else
+#define LS1046A_BOOT_SRC_AND_HDR\
+ "boot_scripts=ls1046ardb_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
+#endif
#ifndef SPL_NO_MISC
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -236,8 +246,7 @@
"console=ttyS0,115200\0" \
CONFIG_MTDPARTS_DEFAULT "\0" \
BOOTENV \
- "boot_scripts=ls1046ardb_boot.scr\0" \
- "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \
+ LS1046A_BOOT_SRC_AND_HDR \
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"env exists devplist || setenv devplist 1; " \
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
new file mode 100644
index 0000000..c874b95
--- /dev/null
+++ b/include/configs/ls1046afrwy.h
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1046AFRWY_H__
+#define __LS1046AFRWY_H__
+
+#include "ls1046a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+
+#define CONFIG_DDR_SPD
+#define SPD_EEPROM_ADDRESS 0x51
+#define CONFIG_SYS_SPD_BUS_NUM 0
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
+#ifndef CONFIG_SPL
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046afrwy/ls1046afrwy_pbi.cfg
+#ifdef CONFIG_EMMC_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046afrwy/ls1046afrwy_rcw_emmc.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046afrwy/ls1046afrwy_rcw_sd.cfg
+#endif
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046afrwy/ls1046afrwy_rcw_qspi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI \
+ board/freescale/ls1046afrwy/ls1046afrwy_qspi_pbi.cfg
+#define CONFIG_SYS_UBOOT_BASE 0x40100000
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
+#endif
+
+#ifndef SPL_NO_IFC
+/* IFC */
+#define CONFIG_FSL_IFC
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+#endif
+
+#define CONFIG_SYS_NAND_BASE 0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_NAND \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
+ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x7) | \
+ FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0xe) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+ FTIM2_NAND_TREH(0xa) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/* IFC Timing Params */
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define I2C_RETIMER_ADDR 0x18
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/
+#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/
+
+/* RTC */
+#define RTC
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
+#define CONFIG_SYS_RTC_BUS_NUM 0
+
+/* PMIC */
+#define CONFIG_POWER
+#ifdef CONFIG_POWER
+#define CONFIG_POWER_I2C
+#endif
+
+/*
+ * Environment
+ */
+#ifndef SPL_NO_ENV
+#define CONFIG_ENV_OVERWRITE
+#endif
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
+#else
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
+#endif
+#endif
+
+/* FMan */
+#ifndef SPL_NO_FMAN
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+
+#define QSGMII_PORT1_PHY_ADDR 0x1c
+#define QSGMII_PORT2_PHY_ADDR 0x1d
+#define QSGMII_PORT3_PHY_ADDR 0x1e
+#define QSGMII_PORT4_PHY_ADDR 0x1f
+
+#define FDT_SEQ_MACADDR_FROM_ENV
+
+#define CONFIG_ETHPRIME "FM1 at DTSEC3"
+#endif
+
+#endif
+
+/* QSPI device */
+#ifndef SPL_NO_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define FSL_QSPI_FLASH_SIZE SZ_64M
+#define FSL_QSPI_FLASH_NUM 1
+#endif
+#endif
+
+#ifndef SPL_NO_MISC
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;;"
+#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#else
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;;"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#endif
+#endif
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1046AFRWY_H__ */
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 2e2ba75..729ad63 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*/
#ifndef __FM_ETH_H__
@@ -41,8 +42,19 @@ enum fm_eth_type {
FM_ETH_10G_E,
};
+/* Historically, on FMan v3 platforms, the first MDIO bus has been used for
+ * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the
+ * TGEC name).
+ *
+ * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,
+ * and no TGEC ports are present on-board.
+ */
#ifdef CONFIG_SYS_FMAN_V3
+#ifdef CONFIG_TARGET_LS1046AFRWY
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#else
#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
+#endif
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
#if (CONFIG_SYS_NUM_FMAN == 2)
#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
--
2.7.4
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