[U-Boot] [PATCH v3 4/4] sysreset: add support for socfpga sysreset

[Simon Goldschmidt]

This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga
to a UCLASS_SYSRESET based dm driver.

A side effect is that gen5 and a10 can now select between cold and warm
reset.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
---

Changes in v3:
- this patch enables the new drivers and drops the ad-hoc code

Changes in v2:
- adapt to patch that separates drivers/sysreset from drivers/misc
  for SPL: select SPL_SYSRESET_SUPPORT, not SPL_DRIVERS_MISC_SUPPORT
- separate gen5/a10 driver from s10 driver
- as sysreset is a function of rstmgr, bind the sysreset drivers
  from rstmgr to get the base address instead of hardcoding it

 arch/arm/Kconfig                      |  4 +++
 arch/arm/mach-socfpga/Makefile        |  1 -
 arch/arm/mach-socfpga/reset_manager.c | 41 ---------------------------
 drivers/reset/reset-socfpga.c         | 19 +++++++++++++
 4 files changed, 23 insertions(+), 42 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/reset_manager.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f91c590f6d..327adbbf0a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -829,10 +829,14 @@ config ARCH_SOCFPGA
 	select SPL_OF_CONTROL
 	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
 	select SPL_SERIAL_SUPPORT
+	select SPL_SYSRESET_SUPPORT
 	select SPL_WATCHDOG_SUPPORT
 	select SUPPORT_SPL
 	select SYS_NS16550
 	select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select SYSRESET
+	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10
 	imply CMD_DM
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e66720447f..fc1181cb27 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,7 +8,6 @@
 obj-y	+= board.o
 obj-y	+= clock_manager.o
 obj-y	+= misc.o
-obj-y	+= reset_manager.o
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y	+= clock_manager_gen5.o
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
deleted file mode 100644
index e0a01ed07a..0000000000
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  Copyright (C) 2013 Altera Corporation <www.altera.com>
- */
-
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/reset_manager.h>
-
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include <asm/arch/mailbox_s10.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-static const struct socfpga_reset_manager *reset_manager_base =
-		(void *)SOCFPGA_RSTMGR_ADDRESS;
-#endif
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
-	/* request a warm reset */
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-	puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
-	mbox_reset_cold();
-#else
-	writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
-	       &reset_manager_base->ctrl);
-#endif
-	/*
-	 * infinite loop here as watchdog will trigger and reset
-	 * the processor
-	 */
-	while (1)
-		;
-}
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index cb8312619f..f49f064574 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -14,6 +14,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/lists.h>
 #include <dm/of_access.h>
 #include <reset-uclass.h>
 #include <linux/bitops.h>
@@ -132,6 +133,23 @@ static int socfpga_reset_remove(struct udevice *dev)
 	return 0;
 }
 
+static int socfpga_reset_bind(struct udevice *dev)
+{
+	int ret;
+	struct udevice *sys_child;
+
+	/*
+	 * The sysreset driver does not have a device node, so bind it here.
+	 * Bind it to the node, too, so that it can get its base address.
+	 */
+	ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
+					 dev->node, &sys_child);
+	if (ret)
+		debug("Warning: No sysreset driver: ret=%d\n", ret);
+
+	return 0;
+}
+
 static const struct udevice_id socfpga_reset_match[] = {
 	{ .compatible = "altr,rst-mgr" },
 	{ /* sentinel */ },
@@ -141,6 +159,7 @@ U_BOOT_DRIVER(socfpga_reset) = {
 	.name = "socfpga-reset",
 	.id = UCLASS_RESET,
 	.of_match = socfpga_reset_match,
+	.bind = socfpga_reset_bind,
 	.probe = socfpga_reset_probe,
 	.priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
 	.ops = &socfpga_reset_ops,
-- 
2.20.1