[U-Boot] [PATCH v3] riscv: Add Microchip MPFS Icicle board support

[Auer, Lukas]

Hi Padmarao,

On Mon, 2019-05-13 at 16:18 +0530, Padmarao Begari wrote:
> This patch adds Microchip MPFS Icicle board support.
> For now, NS16550 serial driver is only enabled.
> The Microchip MPFS Icicle defconfig by default builds
> U-Boot for M-Mode with SMP support.
> 
> Signed-off-by: Padmarao Begari <padmarao.begari at microchip.com>
> ---
> Changes in v3
> - Fix some typos
> - Remove CONFIG_DM, CONFIG_DM_SERIAL, CONFIG_BAUDRATE,
>   CONFIG_SYS_NS16550, CONFIG_SYS_TEXT_BASE and CONFIG_NR_DRAM_BANKS
>   from microchip_mpfs_icicle_defconfig
> - Add config SYS_TEXT_BASE in board kconfig
> - Imply SYS_NS16550 in BOARD_SPECIFIC_OPTIONS
> - select BOARD_EARLY_INIT_F in BOARD_SPECIFIC_OPTIONS
> 
> Changes in v2
> - Fix some typos
> - Rename target board to TARGET_MICROCHIP_ICICLE
> - select CONFIG_BOARD_EARLY_INIT_F in BOARD_SPECIFIC_OPTIONS
> - Remove #ifdef CONFIG_BOARD_EARLY_INIT_F
> ---
>  arch/riscv/Kconfig                        |  4 ++
>  board/microchip/mpfs_icicle/Kconfig       | 26 +++++++++++++
>  board/microchip/mpfs_icicle/MAINTAINERS   |  7 ++++
>  board/microchip/mpfs_icicle/Makefile      |  7 ++++
>  board/microchip/mpfs_icicle/mpfs_icicle.c | 30 +++++++++++++++
>  configs/microchip_mpfs_icicle_defconfig   |  9 +++++
>  include/configs/microchip_mpfs_icicle.h   | 63 +++++++++++++++++++++++++++++++
>  7 files changed, 146 insertions(+)
>  create mode 100644 board/microchip/mpfs_icicle/Kconfig
>  create mode 100644 board/microchip/mpfs_icicle/MAINTAINERS
>  create mode 100644 board/microchip/mpfs_icicle/Makefile
>  create mode 100644 board/microchip/mpfs_icicle/mpfs_icicle.c
>  create mode 100644 configs/microchip_mpfs_icicle_defconfig
>  create mode 100644 include/configs/microchip_mpfs_icicle.h
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 362f3cd..573d6d6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -11,6 +11,9 @@ choice
>  config TARGET_AX25_AE350
>  	bool "Support ax25-ae350"
>  
> +config TARGET_MICROCHIP_ICICLE
> +	bool "Support Microchip PolarFire-SoC Icicle Board"
> +
>  config TARGET_QEMU_VIRT
>  	bool "Support QEMU Virt Board"
>  
> @@ -22,6 +25,7 @@ endchoice
>  # board-specific options below
>  source "board/AndesTech/ax25-ae350/Kconfig"
>  source "board/emulation/qemu-riscv/Kconfig"
> +source "board/microchip/mpfs_icicle/Kconfig"
>  source "board/sifive/fu540/Kconfig"
>  
>  # platform-specific options below
> diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig
> new file mode 100644
> index 0000000..bf8e1a1
> --- /dev/null
> +++ b/board/microchip/mpfs_icicle/Kconfig
> @@ -0,0 +1,26 @@
> +if TARGET_MICROCHIP_ICICLE
> +
> +config SYS_BOARD
> +	default "mpfs_icicle"
> +
> +config SYS_VENDOR
> +	default "microchip"
> +
> +config SYS_CPU
> +	default "generic"
> +
> +config SYS_CONFIG_NAME
> +	default "microchip_mpfs_icicle"
> +
> +config SYS_TEXT_BASE
> +	default 0x80000000 if !RISCV_SMODE
> +	default 0x80200000 if RISCV_SMODE
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +	def_bool y
> +	select GENERIC_RISCV
> +	select BOARD_EARLY_INIT_F
> +	imply SMP
> +	imply SYS_NS16550
> +
> +endif
> diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS
> new file mode 100644
> index 0000000..22f3b97
> --- /dev/null
> +++ b/board/microchip/mpfs_icicle/MAINTAINERS
> @@ -0,0 +1,7 @@
> +Microchip MPFS icicle
> +M:	Padmarao Begari <padmarao.begari at microchip.com>
> +M:	Cyril Jean <cyril.jean at microchip.com>
> +S:	Maintained
> +F:	board/microchip/mpfs_icicle/
> +F:	include/configs/microchip_mpfs_icicle.h
> +F:	configs/microchip_mpfs_icicle_defconfig
> diff --git a/board/microchip/mpfs_icicle/Makefile b/board/microchip/mpfs_icicle/Makefile
> new file mode 100644
> index 0000000..72b0410
> --- /dev/null
> +++ b/board/microchip/mpfs_icicle/Makefile
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2019 Microchip Technology Inc.
> +# Padmarao Begari <padmarao.begari at microchip.com>
> +#
> +
> +obj-y	+= mpfs_icicle.o
> diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c
> new file mode 100644
> index 0000000..0ef2431
> --- /dev/null
> +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Microchip Technology Inc.
> + * Padmarao Begari <padmarao.begari at microchip.com>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/io.h>
> +
> +#define MPFS_SYSREG_SOFT_RESET	((unsigned int *)0x20002088)
> +
> +int board_init(void)
> +{
> +	/* For now nothing to do here. */
> +
> +	return 0;
> +}
> +
> +int board_early_init_f(void)
> +{
> +	unsigned int val;
> +
> +	/* Reset uart peripheral */
> +	val = readl(MPFS_SYSREG_SOFT_RESET);
> +	val = (val & ~(1u << 5u));
> +	writel(val, MPFS_SYSREG_SOFT_RESET);
> +
> +	return 0;
> +}
> diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig
> new file mode 100644
> index 0000000..3fa900a
> --- /dev/null
> +++ b/configs/microchip_mpfs_icicle_defconfig
> @@ -0,0 +1,9 @@
> +CONFIG_RISCV=y
> +CONFIG_ARCH_RV64I=y
> +CONFIG_NR_CPUS=5
> +CONFIG_TARGET_MICROCHIP_ICICLE=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_DISTRO_DEFAULTS=y

Your distro boot configuration in microchip_mpfs_icicle.h is
incomplete. You will have to include the boot command
(config_distro_bootcmd.h), add the mandatory environment variables, and
define the boot target devices. See doc/README.distro for details. You
may also take a look at include/configs/sifive-fu540.h or
include/configs/qemu-riscv.h for examples.

Thanks,
Lukas

> +CONFIG_SYS_PROMPT="RISC-V # "
> +CONFIG_FIT=y
> +CONFIG_OF_PRIOR_STAGE=y
> diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h
> new file mode 100644
> index 0000000..82c7fbb
> --- /dev/null
> +++ b/include/configs/microchip_mpfs_icicle.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019 Microchip Technology Inc.
> + * Padmarao Begari <padmarao.begari at microchip.com>
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * CPU and Board Configuration Options
> + */
> +#define CONFIG_BOOTP_SEND_HOSTNAME
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
> +
> +/*
> + * Print Buffer Size
> + */
> +#define CONFIG_SYS_PBSIZE	\
> +	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +/*
> + * max number of command args
> + */
> +#define CONFIG_SYS_MAXARGS	16
> +
> +/*
> + * Boot Argument Buffer Size
> + */
> +#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
> +
> +/*
> + * Size of malloc() pool
> + * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
> + */
> +#define CONFIG_SYS_MALLOC_LEN	(512 << 10)
> +
> +/*
> + * Physical Memory Map
> + */
> +#define PHYS_SDRAM_0		0x80000000 /* SDRAM Bank #1 */
> +#define PHYS_SDRAM_0_SIZE	0x40000000 /* 1 GB */
> +#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_0
> +
> +/* Init Stack Pointer */
> +#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x200000)
> +
> +#define CONFIG_SYS_LOAD_ADDR	0x80000000 /* SDRAM */
> +
> +/*
> + * memtest works on DRAM
> + */
> +#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
> +#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
> +
> +/* When we use RAM as ENV */
> +#define CONFIG_ENV_SIZE	0x2000
> +
> +#endif /* __CONFIG_H */