[U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Yinbo Zhu <yinbo.zhu at nxp.com>
> Sent: Wednesday, May 15, 2019 3:38 PM
> To: York Sun <york.sun at nxp.com>; u-boot at lists.denx.de; Vabhav Sharma
> <vabhav.sharma at nxp.com>
> Cc: Yinbo Zhu <yinbo.zhu at nxp.com>; Xiaobo Xie <xiaobo.xie at nxp.com>; Jiafei
> Pan <jiafei.pan at nxp.com>; Y.b. Lu <yangbo.lu at nxp.com>; Jagdish Gediya
> <jagdish.gediya at nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha at nxp.com>; Andy Tang <andy.tang at nxp.com>
> Subject: [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second
> eSDHC
> 
> From: Yangbo Lu <yangbo.lu at nxp.com>
> 
> Layerscape began to use two eSDHC controllers, for example, LS1028A. They
> are same IP block with same reference clock.
> This patch is to add clock support for the second eSDHC.
> 
> Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
> Signed-off-by: Yinbo Zhu <yinbo.zhu at nxp.com>
> ---
> Change in v4:
> 		Update the Copyright
> 

Please maintain complete history


>  arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 3 ++-
>  arch/arm/include/asm/arch-fsl-layerscape/clock.h    | 3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> index bc268e207c..0985778ff9 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
> - * Copyright 2014-2015, Freescale Semiconductor, Inc.
> + * Copyright 2014-2015, 2018 Freescale Semiconductor, Inc.

Freescale was there till 2016. After that it was NXP. 

So please start adding NXP copyright

/*
 * Copyright 2017-2019 NXP
 */


--pk