[U-Boot] [PATCHv2 2/8] powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to Kconfig
Z.q. Hou
zhiqiang.hou at nxp.com
Thu May 23 12:22:05 UTC 2019
From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
Use the Kconfig option to select the PCIe reset errata.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V2:
- New patch.
arch/powerpc/cpu/mpc85xx/Kconfig | 21 +++++++++++++++++++++
include/configs/BSC9132QDS.h | 1 -
include/configs/C29XPCIE.h | 1 -
include/configs/MPC8536DS.h | 1 -
include/configs/MPC8544DS.h | 1 -
include/configs/MPC8548CDS.h | 1 -
include/configs/MPC8568MDS.h | 1 -
include/configs/MPC8569MDS.h | 1 -
include/configs/MPC8572DS.h | 1 -
include/configs/P1010RDB.h | 1 -
include/configs/P1022DS.h | 1 -
include/configs/P1023RDB.h | 1 -
include/configs/T208xQDS.h | 1 -
include/configs/T208xRDB.h | 1 -
include/configs/UCP1020.h | 1 -
include/configs/controlcenterd.h | 1 -
include/configs/p1_p2_rdb_pc.h | 1 -
include/configs/p1_twr.h | 1 -
include/configs/sbc8548.h | 1 -
include/configs/xpedite537x.h | 1 -
include/configs/xpedite550x.h | 1 -
21 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 02bc1caa3f..5c23efcf66 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -533,6 +533,7 @@ config ARCH_BSC9132
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_I2C_A004447
select SYS_FSL_ERRATUM_IFC_A002769
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -551,6 +552,7 @@ config ARCH_C29X
select SYS_FSL_DDR_VER_46
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -566,6 +568,7 @@ config ARCH_MPC8536
select FSL_LAW
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -594,6 +597,7 @@ config ARCH_MPC8544
bool
select FSL_LAW
select SYS_FSL_ERRATUM_A005125
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -609,6 +613,7 @@ config ARCH_MPC8548
select SYS_FSL_ERRATUM_NMG_LBC103
select SYS_FSL_ERRATUM_NMG_ETSEC129
select SYS_FSL_ERRATUM_I2C_A004447
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR1
select SYS_FSL_HAS_SEC
@@ -633,6 +638,7 @@ config ARCH_MPC8560
config ARCH_MPC8568
bool
select FSL_LAW
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -643,6 +649,7 @@ config ARCH_MPC8569
select FSL_LAW
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -657,6 +664,7 @@ config ARCH_MPC8572
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_DDR_115
select SYS_FSL_ERRATUM_DDR111_DDR134
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -681,6 +689,7 @@ config ARCH_P1010
select SYS_FSL_ERRATUM_P1010_A003549
select SYS_FSL_ERRATUM_SEC_A003571
select SYS_FSL_ERRATUM_IFC_A003399
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -718,6 +727,7 @@ config ARCH_P1020
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -738,6 +748,7 @@ config ARCH_P1021
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -759,6 +770,7 @@ config ARCH_P1022
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_SATA_A001
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -772,6 +784,7 @@ config ARCH_P1023
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_I2C_A004447
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -786,6 +799,7 @@ config ARCH_P1024
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -807,6 +821,7 @@ config ARCH_P1025
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -824,6 +839,7 @@ config ARCH_P2020
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_ESDHC_A001
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -1079,6 +1095,7 @@ config ARCH_T2080
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
@@ -1103,6 +1120,7 @@ config ARCH_T2081
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
@@ -1439,6 +1457,9 @@ config SYS_P4080_ERRATUM_SERDES_A005
config FSL_PCIE_DISABLE_ASPM
bool
+config FSL_PCIE_RESET
+ bool
+
config SYS_FSL_QORIQ_CHASSIS1
bool
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index f385509daf..3522f03009 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -60,7 +60,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index ebf44b5529..f9b8e446c1 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -69,7 +69,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 1413b3dcfe..bea4021793 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -36,7 +36,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 280b873aee..2cbe855235 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -16,7 +16,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index be600becfe..b37601c794 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -20,7 +20,6 @@
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 9b3485ed4b..bf27427869 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -16,7 +16,6 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index de5a7ca959..e1f29bf107 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -15,7 +15,6 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 13fbbb3044..e3952f423b 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -27,7 +27,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 134ffe5271..88470f69b8 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -127,7 +127,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 3ccfeca890..e785826754 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -90,7 +90,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENABLE_36BIT_PHYS
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 4f6ee22385..1a8b450adc 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -24,7 +24,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#ifndef __ASSEMBLY__
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 9ca384cc0c..7a07679069 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -507,7 +507,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 446e4268ef..77197a1750 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -491,7 +491,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 6a0254a55b..88237ee316 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -17,7 +17,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#if defined(CONFIG_TARTGET_UCP1020T1)
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 1908d35bcc..6d616c3773 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -210,7 +210,6 @@
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 8fda0c1e22..513f6e4767 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -220,7 +220,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 4f48370648..ad1637b5fc 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -35,7 +35,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 9df8604af7..ba613672eb 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -49,7 +49,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif
#ifdef CONFIG_PCIE1
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#endif
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 22dd3c036e..0a87f226f8 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -22,7 +22,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
/*
* Multicore config
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index a7c8dc4e33..0389874609 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -22,7 +22,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
/*
* Multicore config
--
2.17.1
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