[U-Boot] [PATCH v6] ARM: am335x: Add phyCORE AM335x R2 support

[Marek Vasut]

On 5/8/19 1:22 PM, Niel Fourie wrote:

[...]

> diff --git a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
> new file mode 100644
> index 0000000000..76292c43c8
> --- /dev/null
> +++ b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 DENX Software Engineering GmbH
> + */
> +
> +/ {
> +	chosen {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		bootargs = "console=ttyO0,115200 earlyprintk";
> +		stdout-path = &uart0;
> +	};
> +
> +	ocp {
> +		u-boot,dm-pre-reloc;
> +	};
> +};
> +

i2c0 should have dm-pre-reloc here too, see below.

> +&uart0 {
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&mmc1 {
> +	u-boot,dm-pre-reloc;
> +	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
> +};

[...]

> +const struct dpll_params *get_dpll_mpu_params(void)
> +{
> +	int ind = get_sys_clk_index();
> +	int freq = am335x_get_efuse_mpu_max_freq(cdev);
> +
> +	switch (freq) {
> +	case MPUPLL_M_1000:
> +		return &dpll_mpu_opp[ind][5];
> +	case MPUPLL_M_800:
> +		return &dpll_mpu_opp[ind][4];
> +	case MPUPLL_M_720:
> +		return &dpll_mpu_opp[ind][3];
> +	case MPUPLL_M_600:
> +		return &dpll_mpu_opp[ind][2];
> +	case MPUPLL_M_500:
> +		return &dpll_mpu_opp100;
> +	case MPUPLL_M_300:
> +		return &dpll_mpu_opp[ind][0];
> +	}
> +
> +	return &dpll_mpu_opp[ind][0];
> +}
> +
> +void scale_vcores_generic(int freq)

static void ...

> +{
> +	int sil_rev, mpu_vdd;
> +
> +	/*
> +	 * We use a TPS65910 PMIC. For all  MPU frequencies we support we use a
> +	 * CORE voltage of 1.10V. For MPU voltage we need to switch based on
> +	 * the frequency we are running at.
> +	 */
> +	if (power_tps65910_init(0))
> +		return;

This will silently fail without patch [1] and without dm-pre-reloc on
i2c0 node in the DT. For CPUs with higher core clock speed than 600 MHz,
the prcm_init() will set the CPU clock to faster clock frequency without
setting the matching PMIC voltage, and the system will become unstable
in nasty obscure ways.

Phytec always boots with CPU set to 600 MHz, and my suggestion would be
to do the same.

[1] http://patchwork.ozlabs.org/patch/1105418/

> +	/*
> +	 * Depending on MPU clock and PG we will need a different
> +	 * VDD to drive at that speed.
> +	 */
> +	sil_rev = readl(&cdev->deviceid) >> 28;
> +	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
> +
> +	/* Tell the TPS65910 to use i2c */
> +	tps65910_set_i2c_control();
> +
> +	/* First update MPU voltage. */
> +	if (tps65910_voltage_update(MPU, mpu_vdd))
> +		return;
> +
> +	/* Second, update the CORE voltage. */
> +	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
> +		return;
> +}

[...]
-- 
Best regards,
Marek Vasut