[U-Boot] [PATCH 2/3] rockchip: rk3399: Add option to print on UART3.

[Kever Yang]

On 05/07/2019 04:58 PM, Christoph Muellner wrote:
> The RK3399 SPL does not use a pinctrl driver to setup the UART pins.
> Instead it works based on config macros, which set the base address
> of the actual UART block.
>
> Currently the RK3399 SPL support UART0 and UART2.
> This patch adds UART3 in the same way as UART0.
>
> Signed-off-by: Christoph Muellner <christoph.muellner at theobroma-systems.com>

Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>
>  arch/arm/mach-rockchip/rk3399/rk3399.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
> index a7ccd4f3ed..e1f9f8b8ef 100644
> --- a/arch/arm/mach-rockchip/rk3399/rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
> @@ -80,6 +80,14 @@ void board_debug_uart_init(void)
>  	rk_clrsetreg(&grf->gpio2c_iomux,
>  		     GRF_GPIO2C1_SEL_MASK,
>  		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
> +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
> +	/* Enable early UART3 on the RK3399 */
> +	rk_clrsetreg(&grf->gpio3b_iomux,
> +		     GRF_GPIO3B6_SEL_MASK,
> +		     GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
> +	rk_clrsetreg(&grf->gpio3b_iomux,
> +		     GRF_GPIO3B7_SEL_MASK,
> +		     GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
>  #else
>  # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
>  	rk_setreg(&grf->io_vsel, 1 << 0);