[U-Boot] [PATCH v3 3/6] clk: imx8qm: fix usdhc2 clocks

[Marcel Ziswiler]

Trying to bring up uSDHC2 the following error message was observed:

MMC:   imx8_clk_set_rate(Invalid clk ID #60)
imx8_clk_set_rate(Invalid clk ID #60)
usdhc at 5b030000 - probe failed: -22

This commit fixes this by properly setting resp. clocks.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler at toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher at toradex.com>

---

Changes in v3: None
Changes in v2: None

 drivers/clk/imx/clk-imx8qm.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c
index 6b5561e178..a6b09d2109 100644
--- a/drivers/clk/imx/clk-imx8qm.c
+++ b/drivers/clk/imx/clk-imx8qm.c
@@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk)
 		resource = SC_R_SDHC_1;
 		pm_clk = SC_PM_CLK_PER;
 		break;
+	case IMX8QM_SDHC2_IPG_CLK:
+	case IMX8QM_SDHC2_CLK:
+	case IMX8QM_SDHC2_DIV:
+		resource = SC_R_SDHC_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
 	case IMX8QM_UART0_IPG_CLK:
 	case IMX8QM_UART0_CLK:
 		resource = SC_R_UART_0;
@@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
 		resource = SC_R_SDHC_1;
 		pm_clk = SC_PM_CLK_PER;
 		break;
+	case IMX8QM_SDHC2_IPG_CLK:
+	case IMX8QM_SDHC2_CLK:
+	case IMX8QM_SDHC2_DIV:
+		resource = SC_R_SDHC_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
 	case IMX8QM_ENET0_IPG_CLK:
 	case IMX8QM_ENET0_AHB_CLK:
 	case IMX8QM_ENET0_REF_DIV:
@@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable)
 		resource = SC_R_SDHC_1;
 		pm_clk = SC_PM_CLK_PER;
 		break;
+	case IMX8QM_SDHC2_IPG_CLK:
+	case IMX8QM_SDHC2_CLK:
+	case IMX8QM_SDHC2_DIV:
+		resource = SC_R_SDHC_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
 	case IMX8QM_ENET0_IPG_CLK:
 	case IMX8QM_ENET0_AHB_CLK:
 	case IMX8QM_ENET0_REF_DIV:
-- 
2.21.0