[U-Boot] [RFC PATCH 4/5] ram: add SDRAM driver for i.MXRT SoCs

Giulio Benetti giulio.benetti at benettiengineering.com
Mon Nov 4 16:53:54 UTC 2019

On 11/4/19 5:33 PM, Fabio Estevam wrote:
> Hi Giulio,
> On Thu, Oct 31, 2019 at 9:11 AM Giulio Benetti
> <giulio.benetti at benettiengineering.com> wrote:
>> ...in this register and the next one there are parameters like CKEOFF
>> and ACT2PRE impossible to lead to classic tXXX sdram timing parameters.
>> I've done this way inspired by stm32-sdram, but maybe U should go back
>> using i.MXRT names(i.e. PRE2ACT instead of tRP) and list all possible
>> useful registers in DM as I've done for tRP etc.
>> What do you think?
> I think it is OK to use the i.MXRT names.


> #define TWR_1                        0x0
>>> +#define TWR_2                        0x1
>>> +#define TWR_3                        0x2
>>> +#define TWR_4                        0x3
>>> +#define TWR_5                        0x4
>>> +#define TWR_6                        0x5
>>> +#define TWR_7                        0x6
>>> +#define TWR_8                        0x7
>>> +#define TWR_9                        0x8
>>> +#define TWR_10                       0x9
>>> +#define TWR_11                       0xA
>>> +#define TWR_12                       0xB
>>> +#define TWR_13                       0xC
>>> +#define TWR_14                       0xD
>>> +#define TWR_15                       0xE
>>> +#define TWR_16                       0xF
>>> +
>>> +#endif
>> ...is it ok listing every possible value for DM parameter?
>> I mean, some of them would be 8-bit, this would mean having 256 cases,
>> that sound very ugly to me.
> It doesn't seem necessary to write all 256 cases. I would suggest to
> write the direct hex number.

Well, thanks a lot!

Best regards
Giulio Benetti
Benetti Engineering sas

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