[U-Boot] [PATCH v2 1/9] arm: rockchip: Add RK3308 SOC support
Kever Yang
kever.yang at rock-chips.com
Thu Nov 7 09:30:52 UTC 2019
On 2019/10/30 下午4:11, Andy Yan wrote:
> RK3308 is a quad Cortex A35 based SOC with rich audio
> interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
> designed for intelligent voice interaction and audio
> input/output processing.
>
> Signed-off-by: Andy Yan <andy.yan at rock-chips.com>
Reviewed-by: Kever Yang<kever.yang at rock-chips.com>
Thanks,
- Kever
>
> ---
>
> Changes in v2: None
>
> arch/arm/include/asm/arch-rk3308/boot0.h | 11 +
> arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 290 ++++++++++++++++++
> arch/arm/include/asm/arch-rk3308/gpio.h | 11 +
> arch/arm/include/asm/arch-rk3308/grf_rk3308.h | 197 ++++++++++++
> arch/arm/mach-rockchip/Kconfig | 24 ++
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3308/Kconfig | 14 +
> arch/arm/mach-rockchip/rk3308/Makefile | 9 +
> arch/arm/mach-rockchip/rk3308/clk_rk3308.c | 31 ++
> arch/arm/mach-rockchip/rk3308/rk3308.c | 175 +++++++++++
> arch/arm/mach-rockchip/rk3308/syscon_rk3308.c | 20 ++
> include/configs/rk3308_common.h | 58 ++++
> 12 files changed, 841 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
> create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
> create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
> create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
> create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
> create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
> create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
> create mode 100644 include/configs/rk3308_common.h
>
> diff --git a/arch/arm/include/asm/arch-rk3308/boot0.h b/arch/arm/include/asm/arch-rk3308/boot0.h
> new file mode 100644
> index 0000000000..2e78b074ad
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3308/boot0.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2019 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __ASM_ARCH_BOOT0_H__
> +#define __ASM_ARCH_BOOT0_H__
> +
> +#include <asm/arch-rockchip/boot0.h>
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
> new file mode 100644
> index 0000000000..a14b64cdb3
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
> @@ -0,0 +1,290 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
> + */
> +#ifndef _ASM_ARCH_CRU_RK3308_H
> +#define _ASM_ARCH_CRU_RK3308_H
> +
> +#include <common.h>
> +
> +#define MHz 1000000
> +#define OSC_HZ (24 * MHz)
> +
> +#define APLL_HZ (816 * MHz)
> +
> +#define CORE_ACLK_HZ 408000000
> +#define CORE_DBG_HZ 204000000
> +
> +#define BUS_ACLK_HZ 200000000
> +#define BUS_HCLK_HZ 100000000
> +#define BUS_PCLK_HZ 100000000
> +
> +#define PERI_ACLK_HZ 200000000
> +#define PERI_HCLK_HZ 100000000
> +#define PERI_PCLK_HZ 100000000
> +
> +#define AUDIO_HCLK_HZ 100000000
> +#define AUDIO_PCLK_HZ 100000000
> +
> +#define RK3308_PLL_CON(x) ((x) * 0x4)
> +#define RK3308_MODE_CON 0xa0
> +
> +/* RK3308 pll id */
> +enum rk3308_pll_id {
> + APLL,
> + DPLL,
> + VPLL0,
> + VPLL1,
> + PLL_COUNT,
> +};
> +
> +struct rk3308_clk_info {
> + unsigned long id;
> + char *name;
> +};
> +
> +/* Private data for the clock driver - used by rockchip_get_cru() */
> +struct rk3308_clk_priv {
> + struct rk3308_cru *cru;
> + ulong armclk_hz;
> + ulong dpll_hz;
> + ulong vpll0_hz;
> + ulong vpll1_hz;
> +};
> +
> +struct rk3308_cru {
> + struct rk3308_pll {
> + unsigned int con0;
> + unsigned int con1;
> + unsigned int con2;
> + unsigned int con3;
> + unsigned int con4;
> + unsigned int reserved0[3];
> + } pll[4];
> + unsigned int reserved1[8];
> + unsigned int mode;
> + unsigned int misc;
> + unsigned int reserved2[2];
> + unsigned int glb_cnt_th;
> + unsigned int glb_rst_st;
> + unsigned int glb_srst_fst;
> + unsigned int glb_srst_snd;
> + unsigned int glb_rst_con;
> + unsigned int pll_lock;
> + unsigned int reserved3[6];
> + unsigned int hwffc_con0;
> + unsigned int reserved4;
> + unsigned int hwffc_th;
> + unsigned int hwffc_intst;
> + unsigned int apll_con0_s;
> + unsigned int apll_con1_s;
> + unsigned int clksel_con0_s;
> + unsigned int reserved5;
> + unsigned int clksel_con[74];
> + unsigned int reserved6[54];
> + unsigned int clkgate_con[15];
> + unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
> + unsigned int ssgtbl[32];
> + unsigned int softrst_con[10];
> + unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
> + unsigned int sdmmc_con[2];
> + unsigned int sdio_con[2];
> + unsigned int emmc_con[2];
> +};
> +
> +enum {
> + /* PLLCON0*/
> + PLL_BP_SHIFT = 15,
> + PLL_POSTDIV1_SHIFT = 12,
> + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
> + PLL_FBDIV_SHIFT = 0,
> + PLL_FBDIV_MASK = 0xfff,
> +
> + /* PLLCON1 */
> + PLL_PDSEL_SHIFT = 15,
> + PLL_PD1_SHIFT = 14,
> + PLL_PD_SHIFT = 13,
> + PLL_PD_MASK = 1 << PLL_PD_SHIFT,
> + PLL_DSMPD_SHIFT = 12,
> + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
> + PLL_LOCK_STATUS_SHIFT = 10,
> + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
> + PLL_POSTDIV2_SHIFT = 6,
> + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
> + PLL_REFDIV_SHIFT = 0,
> + PLL_REFDIV_MASK = 0x3f,
> +
> + /* PLLCON2 */
> + PLL_FOUT4PHASEPD_SHIFT = 27,
> + PLL_FOUTVCOPD_SHIFT = 26,
> + PLL_FOUTPOSTDIVPD_SHIFT = 25,
> + PLL_DACPD_SHIFT = 24,
> + PLL_FRAC_DIV = 0xffffff,
> +
> + /* CRU_MODE */
> + PLLMUX_FROM_XIN24M = 0,
> + PLLMUX_FROM_PLL,
> + PLLMUX_FROM_RTC32K,
> + USBPHY480M_MODE_SHIFT = 8,
> + USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
> + VPLL1_MODE_SHIFT = 6,
> + VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT,
> + VPLL0_MODE_SHIFT = 4,
> + VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT,
> + DPLL_MODE_SHIFT = 2,
> + DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
> + APLL_MODE_SHIFT = 0,
> + APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
> +
> + /* CRU_CLK_SEL0_CON */
> + CORE_ACLK_DIV_SHIFT = 12,
> + CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT,
> + CORE_DBG_DIV_SHIFT = 8,
> + CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT,
> + CORE_CLK_PLL_SEL_SHIFT = 6,
> + CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT,
> + CORE_CLK_PLL_SEL_APLL = 0,
> + CORE_CLK_PLL_SEL_VPLL0,
> + CORE_CLK_PLL_SEL_VPLL1,
> + CORE_DIV_CON_SHIFT = 0,
> + CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
> +
> + /* CRU_CLK_SEL5_CON */
> + BUS_PLL_SEL_SHIFT = 6,
> + BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT,
> + BUS_PLL_SEL_DPLL = 0,
> + BUS_PLL_SEL_VPLL0,
> + BUS_PLL_SEL_VPLL1,
> + BUS_ACLK_DIV_SHIFT = 0,
> + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
> +
> + /* CRU_CLK_SEL6_CON */
> + BUS_PCLK_DIV_SHIFT = 8,
> + BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT,
> + BUS_HCLK_DIV_SHIFT = 0,
> + BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
> +
> + /* CRU_CLK_SEL7_CON */
> + CRYPTO_APK_SEL_SHIFT = 14,
> + CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
> + CRYPTO_PLL_SEL_DPLL = 0,
> + CRYPTO_PLL_SEL_VPLL0,
> + CRYPTO_PLL_SEL_VPLL1 = 0,
> + CRYPTO_APK_DIV_SHIFT = 8,
> + CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
> + CRYPTO_PLL_SEL_SHIFT = 6,
> + CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
> + CRYPTO_DIV_SHIFT = 0,
> + CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
> +
> + /* CRU_CLK_SEL8_CON */
> + DCLK_VOP_SEL_SHIFT = 14,
> + DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT,
> + DCLK_VOP_SEL_DIVOUT = 0,
> + DCLK_VOP_SEL_FRACOUT,
> + DCLK_VOP_SEL_24M,
> + DCLK_VOP_PLL_SEL_SHIFT = 10,
> + DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT,
> + DCLK_VOP_PLL_SEL_DPLL = 0,
> + DCLK_VOP_PLL_SEL_VPLL0,
> + DCLK_VOP_PLL_SEL_VPLL1,
> + DCLK_VOP_DIV_SHIFT = 0,
> + DCLK_VOP_DIV_MASK = 0xff,
> +
> + /* CRU_CLK_SEL25_CON */
> + /* CRU_CLK_SEL26_CON */
> + /* CRU_CLK_SEL27_CON */
> + /* CRU_CLK_SEL28_CON */
> + CLK_I2C_PLL_SEL_SHIFT = 14,
> + CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT,
> + CLK_I2C_PLL_SEL_DPLL = 0,
> + CLK_I2C_PLL_SEL_VPLL0,
> + CLK_I2C_PLL_SEL_24M,
> + CLK_I2C_DIV_CON_SHIFT = 0,
> + CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT,
> +
> + /* CRU_CLK_SEL29_CON */
> + CLK_PWM_PLL_SEL_SHIFT = 14,
> + CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT,
> + CLK_PWM_PLL_SEL_DPLL = 0,
> + CLK_PWM_PLL_SEL_VPLL0,
> + CLK_PWM_PLL_SEL_24M,
> + CLK_PWM_DIV_CON_SHIFT = 0,
> + CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
> +
> + /* CRU_CLK_SEL30_CON */
> + /* CRU_CLK_SEL31_CON */
> + /* CRU_CLK_SEL32_CON */
> + CLK_SPI_PLL_SEL_SHIFT = 14,
> + CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT,
> + CLK_SPI_PLL_SEL_DPLL = 0,
> + CLK_SPI_PLL_SEL_VPLL0,
> + CLK_SPI_PLL_SEL_24M,
> + CLK_SPI_DIV_CON_SHIFT = 0,
> + CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
> +
> + /* CRU_CLK_SEL34_CON */
> + CLK_SARADC_DIV_CON_SHIFT = 0,
> + CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT,
> +
> + /* CRU_CLK_SEL36_CON */
> + PERI_PLL_SEL_SHIFT = 6,
> + PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT,
> + PERI_PLL_DPLL = 0,
> + PERI_PLL_VPLL0,
> + PERI_PLL_VPLL1,
> + PERI_ACLK_DIV_SHIFT = 0,
> + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
> +
> + /* CRU_CLK_SEL37_CON */
> + PERI_PCLK_DIV_SHIFT = 8,
> + PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT,
> + PERI_HCLK_DIV_SHIFT = 0,
> + PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
> +
> + /* CRU_CLKSEL41_CON */
> + EMMC_CLK_SEL_SHIFT = 15,
> + EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
> + EMMC_CLK_SEL_EMMC = 0,
> + EMMC_CLK_SEL_EMMC_DIV50,
> + EMMC_PLL_SHIFT = 8,
> + EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT,
> + EMMC_SEL_DPLL = 0,
> + EMMC_SEL_VPLL0,
> + EMMC_SEL_VPLL1,
> + EMMC_SEL_24M,
> + EMMC_DIV_SHIFT = 0,
> + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
> +
> + /* CRU_CLKSEL43_CON */
> + MAC_CLK_SPEED_SEL_SHIFT = 15,
> + MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT,
> + MAC_CLK_SPEED_SEL_10M = 0,
> + MAC_CLK_SPEED_SEL_100M,
> + MAC_CLK_SOURCE_SEL_SHIFT = 14,
> + MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT,
> + MAC_CLK_SOURCE_SEL_INTERNAL = 0,
> + MAC_CLK_SOURCE_SEL_EXTERNAL,
> + MAC_PLL_SHIFT = 6,
> + MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT,
> + MAC_SEL_DPLL = 0,
> + MAC_SEL_VPLL0,
> + MAC_SEL_VPLL1,
> + MAC_DIV_SHIFT = 0,
> + MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT,
> +
> + /* CRU_CLK_SEL45_CON */
> + AUDIO_PCLK_DIV_SHIFT = 8,
> + AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT,
> + AUDIO_PLL_SEL_SHIFT = 6,
> + AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT,
> + AUDIO_PLL_VPLL0 = 0,
> + AUDIO_PLL_VPLL1,
> + AUDIO_PLL_24M,
> + AUDIO_HCLK_DIV_SHIFT = 0,
> + AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT,
> +};
> +
> +check_member(rk3308_cru, emmc_con[1], 0x494);
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rk3308/gpio.h b/arch/arm/include/asm/arch-rk3308/gpio.h
> new file mode 100644
> index 0000000000..eca79d5159
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3308/gpio.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2019 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __ASM_ARCH_GPIO_H__
> +#define __ASM_ARCH_GPIO_H__
> +
> +#include <asm/arch-rockchip/gpio.h>
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rk3308/grf_rk3308.h b/arch/arm/include/asm/arch-rk3308/grf_rk3308.h
> new file mode 100644
> index 0000000000..3e68626d3e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3308/grf_rk3308.h
> @@ -0,0 +1,197 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + *Copyright 2019 Rockchip Electronics Co., Ltd.
> + */
> +#ifndef _ASM_ARCH_GRF_rk3308_H
> +#define _ASM_ARCH_GRF_rk3308_H
> +
> +#include <common.h>
> +
> +struct rk3308_grf {
> + unsigned int gpio0a_iomux;
> + unsigned int reserved0;
> + unsigned int gpio0b_iomux;
> + unsigned int reserved1;
> + unsigned int gpio0c_iomux;
> + unsigned int reserved2[3];
> + unsigned int gpio1a_iomux;
> + unsigned int reserved3;
> + unsigned int gpio1bl_iomux;
> + unsigned int gpio1bh_iomux;
> + unsigned int gpio1cl_iomux;
> + unsigned int gpio1ch_iomux;
> + unsigned int gpio1d_iomux;
> + unsigned int reserved4;
> + unsigned int gpio2a_iomux;
> + unsigned int reserved5;
> + unsigned int gpio2b_iomux;
> + unsigned int reserved6;
> + unsigned int gpio2c_iomux;
> + unsigned int reserved7[3];
> + unsigned int gpio3a_iomux;
> + unsigned int reserved8;
> + unsigned int gpio3b_iomux;
> + unsigned int reserved9[5];
> + unsigned int gpio4a_iomux;
> + unsigned int reserved33;
> + unsigned int gpio4b_iomux;
> + unsigned int reserved10;
> + unsigned int gpio4c_iomux;
> + unsigned int reserved11;
> + unsigned int gpio4d_iomux;
> + unsigned int reserved34;
> + unsigned int gpio0a_p;
> + unsigned int gpio0b_p;
> + unsigned int gpio0c_p;
> + unsigned int reserved12;
> + unsigned int gpio1a_p;
> + unsigned int gpio1b_p;
> + unsigned int gpio1c_p;
> + unsigned int gpio1d_p;
> + unsigned int gpio2a_p;
> + unsigned int gpio2b_p;
> + unsigned int gpio2c_p;
> + unsigned int reserved13;
> + unsigned int gpio3a_p;
> + unsigned int gpio3b_p;
> + unsigned int reserved14[2];
> + unsigned int gpio4a_p;
> + unsigned int gpio4b_p;
> + unsigned int gpio4c_p;
> + unsigned int gpio4d_p;
> + unsigned int reserved15[(0x100 - 0xec) / 4 - 1];
> + unsigned int gpio0a_e;
> + unsigned int gpio0b_e;
> + unsigned int gpio0c_e;
> + unsigned int reserved16;
> + unsigned int gpio1a_e;
> + unsigned int gpio1b_e;
> + unsigned int gpio1c_e;
> + unsigned int gpio1d_e;
> + unsigned int gpio2a_e;
> + unsigned int gpio2b_e;
> + unsigned int gpio2c_e;
> + unsigned int reserved17;
> + unsigned int gpio3a_e;
> + unsigned int gpio3b_e;
> + unsigned int reserved18[2];
> + unsigned int gpio4a_e;
> + unsigned int gpio4b_e;
> + unsigned int gpio4c_e;
> + unsigned int gpio4d_e;
> + unsigned int gpio0a_sr;
> + unsigned int gpio0b_sr;
> + unsigned int gpio0c_sr;
> + unsigned int reserved19;
> + unsigned int gpio1a_sr;
> + unsigned int gpio1b_sr;
> + unsigned int gpio1c_sr;
> + unsigned int gpio1d_sr;
> + unsigned int gpio2a_sr;
> + unsigned int gpio2b_sr;
> + unsigned int gpio2c_sr;
> + unsigned int reserved20;
> + unsigned int gpio3a_sr;
> + unsigned int gpio3b_sr;
> + unsigned int reserved21[2];
> + unsigned int gpio4a_sr;
> + unsigned int gpio4b_sr;
> + unsigned int gpio4c_sr;
> + unsigned int gpio4d_sr;
> + unsigned int gpio0a_smt;
> + unsigned int gpio0b_smt;
> + unsigned int gpio0c_smt;
> + unsigned int reserved22;
> + unsigned int gpio1a_smt;
> + unsigned int gpio1b_smt;
> + unsigned int gpio1c_smt;
> + unsigned int gpio1d_smt;
> + unsigned int gpio2a_smt;
> + unsigned int gpio2b_smt;
> + unsigned int gpio2c_smt;
> + unsigned int reserved23;
> + unsigned int gpio3a_smt;
> + unsigned int gpio3b_smt;
> + unsigned int reserved35[2];
> + unsigned int gpio4a_smt;
> + unsigned int gpio4b_smt;
> + unsigned int gpio4c_smt;
> + unsigned int gpio4d_smt;
> + unsigned int reserved24[(0x300 - 0x1EC) / 4 - 1];
> + unsigned int soc_con0;
> + unsigned int soc_con1;
> + unsigned int soc_con2;
> + unsigned int soc_con3;
> + unsigned int soc_con4;
> + unsigned int soc_con5;
> + unsigned int soc_con6;
> + unsigned int soc_con7;
> + unsigned int soc_con8;
> + unsigned int soc_con9;
> + unsigned int soc_con10;
> + unsigned int reserved25[(0x380 - 0x328) / 4 - 1];
> + unsigned int soc_status0;
> + unsigned int reserved26[(0x400 - 0x380) / 4 - 1];
> + unsigned int cpu_con0;
> + unsigned int cpu_con1;
> + unsigned int cpu_con2;
> + unsigned int reserved27[(0x420 - 0x408) / 4 - 1];
> + unsigned int cpu_status0;
> + unsigned int cpu_status1;
> + unsigned int reserved28[(0x440 - 0x424) / 4 - 1];
> + unsigned int pvtm_con0;
> + unsigned int pvtm_con1;
> + unsigned int pvtm_status0;
> + unsigned int pvtm_status1;
> + unsigned int reserved29[(0x460 - 0x44C) / 4 - 1];
> + unsigned int tsadc_tbl;
> + unsigned int tsadc_tbh;
> + unsigned int reserved30[(0x480 - 0x464) / 4 - 1];
> + unsigned int host0_con0;
> + unsigned int host0_con1;
> + unsigned int otg_con0;
> + unsigned int host0_status0;
> + unsigned int reserved31[(0x4a0 - 0x48C) / 4 - 1];
> + unsigned int mac_con0;
> + unsigned int upctrl_con0;
> + unsigned int upctrl_status0;
> + unsigned int reserved32[(0x500 - 0x4A8) / 4 - 1];
> + unsigned int os_reg0;
> + unsigned int os_reg1;
> + unsigned int os_reg2;
> + unsigned int os_reg3;
> + unsigned int os_reg4;
> + unsigned int os_reg5;
> + unsigned int os_reg6;
> + unsigned int os_reg7;
> + unsigned int os_reg8;
> + unsigned int os_reg9;
> + unsigned int os_reg10;
> + unsigned int os_reg11;
> + unsigned int reserved38[(0x600 - 0x52c) / 4 - 1];
> + unsigned int soc_con12;
> + unsigned int reserved39;
> + unsigned int soc_con13;
> + unsigned int soc_con14;
> + unsigned int soc_con15;
> + unsigned int reserved40[(0x800 - 0x610) / 4 - 1];
> + unsigned int chip_id;
> +};
> +check_member(rk3308_grf, gpio0a_p, 0xa0);
> +
> +struct rk3308_sgrf {
> + unsigned int soc_con0;
> + unsigned int soc_con1;
> + unsigned int con_tzma_r0size;
> + unsigned int con_secure0;
> + unsigned int reserved0;
> + unsigned int clk_timer_en;
> + unsigned int clkgat_con;
> + unsigned int fastboot_addr;
> + unsigned int fastboot_en;
> + unsigned int reserved1[(0x30 - 0x24) / 4];
> + unsigned int srst_con;
> +};
> +check_member(rk3308_sgrf, fastboot_en, 0x20);
> +
> +#endif
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index f5a80b4f0c..fb199bc910 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -105,6 +105,29 @@ config ROCKCHIP_RK3288
> and video codec support. Peripherals include Gigabit Ethernet,
> USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK3308
> + bool "Support Rockchip RK3308"
> + select ARM64
> + select DEBUG_UART_BOARD_INIT
> + select SUPPORT_SPL
> + select SUPPORT_TPL
> + select SPL
> + select SPL_ATF
> + select SPL_ATF_NO_PLATFORM_PARAM
> + select SPL_LOAD_FIT
> + imply ROCKCHIP_COMMON_BOARD
> + imply SPL_ROCKCHIP_COMMON_BOARD
> + imply SPL_CLK
> + imply SPL_REGMAP
> + imply SPL_SYSCON
> + imply SPL_RAM
> + imply SPL_SERIAL_SUPPORT
> + imply TPL_SERIAL_SUPPORT
> + imply SPL_SEPARATE_BSS
> + help
> + The Rockchip RK3308 is a ARM-based Soc which embedded with quad
> + Cortex-A35 and highly integrated audio interfaces.
> +
> config ROCKCHIP_RK3328
> bool "Support Rockchip RK3328"
> select ARM64
> @@ -320,6 +343,7 @@ source "arch/arm/mach-rockchip/rk3128/Kconfig"
> source "arch/arm/mach-rockchip/rk3188/Kconfig"
> source "arch/arm/mach-rockchip/rk322x/Kconfig"
> source "arch/arm/mach-rockchip/rk3288/Kconfig"
> +source "arch/arm/mach-rockchip/rk3308/Kconfig"
> source "arch/arm/mach-rockchip/rk3328/Kconfig"
> source "arch/arm/mach-rockchip/rk3368/Kconfig"
> source "arch/arm/mach-rockchip/rk3399/Kconfig"
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 45d9b06233..974fbc138c 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
> obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
> +obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
> obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
> obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
> diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig
> new file mode 100644
> index 0000000000..9c09661595
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3308/Kconfig
> @@ -0,0 +1,14 @@
> +if ROCKCHIP_RK3308
> +
> +config SYS_SOC
> + default "rk3308"
> +
> +config SYS_MALLOC_F_LEN
> + default 0x400
> +
> +config SPL_SERIAL_SUPPORT
> + default y
> +
> +config ROCKCHIP_BOOT_MODE_REG
> + default 0xff000500
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3308/Makefile b/arch/arm/mach-rockchip/rk3308/Makefile
> new file mode 100644
> index 0000000000..ce4d44bb34
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3308/Makefile
> @@ -0,0 +1,9 @@
> +#
> +# (C) Copyright 2018 Rockchip Electronics Co., Ltd.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += syscon_rk3308.o
> +obj-y += rk3308.o
> +obj-y += clk_rk3308.o
> diff --git a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c
> new file mode 100644
> index 0000000000..51b43153e8
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch/cru_rk3308.h>
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> + return uclass_get_device_by_driver(UCLASS_CLK,
> + DM_GET_DRIVER(rockchip_rk3308_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> + struct rk3308_clk_priv *priv;
> + struct udevice *dev;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + priv = dev_get_priv(dev);
> +
> + return priv->cru;
> +}
> diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c
> new file mode 100644
> index 0000000000..f27f9e8c0b
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
> @@ -0,0 +1,175 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + *Copyright (c) 2018 Rockchip Electronics Co., Ltd
> + */
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/grf_rk3308.h>
> +#include <asm/arch-rockchip/hardware.h>
> +#include <asm/gpio.h>
> +#include <debug_uart.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#include <asm/armv8/mmu.h>
> +static struct mm_region rk3308_mem_map[] = {
> + {
> + .virt = 0x0UL,
> + .phys = 0x0UL,
> + .size = 0xff000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + .virt = 0xff000000UL,
> + .phys = 0xff000000UL,
> + .size = 0x01000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = rk3308_mem_map;
> +
> +#define GRF_BASE 0xff000000
> +#define SGRF_BASE 0xff2b0000
> +
> +enum {
> + GPIO1C7_SHIFT = 8,
> + GPIO1C7_MASK = GENMASK(11, 8),
> + GPIO1C7_GPIO = 0,
> + GPIO1C7_UART1_RTSN,
> + GPIO1C7_UART2_TX_M0,
> + GPIO1C7_SPI2_MOSI,
> + GPIO1C7_JTAG_TMS,
> +
> + GPIO1C6_SHIFT = 4,
> + GPIO1C6_MASK = GENMASK(7, 4),
> + GPIO1C6_GPIO = 0,
> + GPIO1C6_UART1_CTSN,
> + GPIO1C6_UART2_RX_M0,
> + GPIO1C6_SPI2_MISO,
> + GPIO1C6_JTAG_TCLK,
> +
> + GPIO4D3_SHIFT = 6,
> + GPIO4D3_MASK = GENMASK(7, 6),
> + GPIO4D3_GPIO = 0,
> + GPIO4D3_SDMMC_D3,
> + GPIO4D3_UART2_TX_M1,
> +
> + GPIO4D2_SHIFT = 4,
> + GPIO4D2_MASK = GENMASK(5, 4),
> + GPIO4D2_GPIO = 0,
> + GPIO4D2_SDMMC_D2,
> + GPIO4D2_UART2_RX_M1,
> +
> + UART2_IO_SEL_SHIFT = 2,
> + UART2_IO_SEL_MASK = GENMASK(3, 2),
> + UART2_IO_SEL_M0 = 0,
> + UART2_IO_SEL_M1,
> + UART2_IO_SEL_USB,
> +
> + GPIO3B3_SEL_SRC_CTRL_SHIFT = 7,
> + GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7),
> + GPIO3B3_SEL_SRC_CTRL_IOMUX = 0,
> + GPIO3B3_SEL_SRC_CTRL_SEL_PLUS,
> +
> + GPIO3B3_SEL_PLUS_SHIFT = 4,
> + GPIO3B3_SEL_PLUS_MASK = GENMASK(6, 4),
> + GPIO3B3_SEL_PLUS_GPIO3_B3 = 0,
> + GPIO3B3_SEL_PLUS_FLASH_ALE,
> + GPIO3B3_SEL_PLUS_EMMC_PWREN,
> + GPIO3B3_SEL_PLUS_SPI1_CLK,
> + GPIO3B3_SEL_PLUS_LCDC_D23_M1,
> +
> + GPIO3B2_SEL_SRC_CTRL_SHIFT = 3,
> + GPIO3B2_SEL_SRC_CTRL_MASK = BIT(3),
> + GPIO3B2_SEL_SRC_CTRL_IOMUX = 0,
> + GPIO3B2_SEL_SRC_CTRL_SEL_PLUS,
> +
> + GPIO3B2_SEL_PLUS_SHIFT = 0,
> + GPIO3B2_SEL_PLUS_MASK = GENMASK(2, 0),
> + GPIO3B2_SEL_PLUS_GPIO3_B2 = 0,
> + GPIO3B2_SEL_PLUS_FLASH_RDN,
> + GPIO3B2_SEL_PLUS_EMMC_RSTN,
> + GPIO3B2_SEL_PLUS_SPI1_MISO,
> + GPIO3B2_SEL_PLUS_LCDC_D22_M1,
> +};
> +
> +enum {
> + IOVSEL3_CTRL_SHIFT = 8,
> + IOVSEL3_CTRL_MASK = BIT(8),
> + VCCIO3_SEL_BY_GPIO = 0,
> + VCCIO3_SEL_BY_IOVSEL3,
> +
> + IOVSEL3_SHIFT = 3,
> + IOVSEL3_MASK = BIT(3),
> + VCCIO3_3V3 = 0,
> + VCCIO3_1V8,
> +};
> +
> +/*
> + * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
> + * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
> + * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
> + * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
> + * for other usage.
> + */
> +
> +#define GPIO0_A4 4
> +
> +int rk_board_init(void)
> +{
> + static struct rk3308_grf * const grf = (void *)GRF_BASE;
> + u32 val;
> + int ret;
> +
> + ret = gpio_request(GPIO0_A4, "gpio0_a4");
> + if (ret < 0) {
> + printf("request for gpio0_a4 failed:%d\n", ret);
> + return 0;
> + }
> +
> + gpio_direction_input(GPIO0_A4);
> +
> + if (gpio_get_value(GPIO0_A4))
> + val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
> + VCCIO3_1V8 << IOVSEL3_SHIFT;
> + else
> + val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
> + VCCIO3_3V3 << IOVSEL3_SHIFT;
> + rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
> +
> + gpio_free(GPIO0_A4);
> + return 0;
> +}
> +
> +#if defined(CONFIG_DEBUG_UART)
> +__weak void board_debug_uart_init(void)
> +{
> + static struct rk3308_grf * const grf = (void *)GRF_BASE;
> +
> + /* Enable early UART2 channel m1 on the rk3308 */
> + rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
> + UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
> + rk_clrsetreg(&grf->gpio4d_iomux,
> + GPIO4D3_MASK | GPIO4D2_MASK,
> + GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
> + GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
> +}
> +#endif
> +
> +#if defined(CONFIG_SPL_BUILD)
> +int arch_cpu_init(void)
> +{
> + static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
> +
> + /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
> + rk_clrreg(&sgrf->con_secure0, 0x2b83);
> +
> + return 0;
> +}
> +#endif
> diff --git a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
> new file mode 100644
> index 0000000000..b380ff5723
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2018 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +
> +static const struct udevice_id rk3308_syscon_ids[] = {
> + { .compatible = "rockchip,rk3308-grf", .data = ROCKCHIP_SYSCON_GRF },
> + { }
> +};
> +
> +U_BOOT_DRIVER(syscon_rk3308) = {
> + .name = "rk3308_syscon",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3308_syscon_ids,
> +};
> diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
> new file mode 100644
> index 0000000000..a67d3d7d1b
> --- /dev/null
> +++ b/include/configs/rk3308_common.h
> @@ -0,0 +1,58 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __CONFIG_RK3308_COMMON_H
> +#define __CONFIG_RK3308_COMMON_H
> +
> +#include "rockchip-common.h"
> +
> +#define CONFIG_SYS_CBSIZE 1024
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
> +#define CONFIG_SYS_NAND_PAGE_COUNT 64
> +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
> +#define CONFIG_SPL_MAX_SIZE 0x20000
> +#define CONFIG_SPL_BSS_START_ADDR 0x00400000
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
> +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
> +
> +#define CONFIG_SYS_NS16550_MEM32
> +
> +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0
> +#define CONFIG_IRAM_BASE 0xfff80000
> +#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
> +#define CONFIG_SYS_LOAD_ADDR 0x00C00800
> +#define CONFIG_SPL_STACK 0x00400000
> +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
> +
> +#define COUNTER_FREQUENCY 24000000
> +
> +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
> +
> +#define CONFIG_SYS_SDRAM_BASE 0
> +#define SDRAM_MAX_SIZE 0xff000000
> +#define SDRAM_BANK_SIZE (2UL << 30)
> +
> +#ifndef CONFIG_SPL_BUILD
> +
> +#define ENV_MEM_LAYOUT_SETTINGS \
> + "scriptaddr=0x00500000\0" \
> + "pxefile_addr_r=0x00600000\0" \
> + "fdt_addr_r=0x01f00000\0" \
> + "kernel_addr_r=0x00680000\0" \
> + "ramdisk_addr_r=0x04000000\0"
> +
> +#include <config_distro_bootcmd.h>
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + ENV_MEM_LAYOUT_SETTINGS \
> + "partitions=" PARTS_DEFAULT \
> + ROCKCHIP_DEVICE_SETTINGS \
> + BOOTENV
> +
> +#endif
> +
> +#endif
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