[U-Boot] [PATCH v2] spi: cadence_qspi: support DM_CLK

[Simon Goldschmidt]

Vignesh Raghavendra <vigneshr at ti.com> schrieb am Mo., 11. Nov. 2019, 05:22:

>
>
> On 10/11/19 5:11 PM, Vignesh Raghavendra wrote:
> > Hi Simon,
> >
> > On 24-Oct-19 11:53 PM, Simon Goldschmidt wrote:
> >> From: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> >>
> >> Support loading clk speed via DM instead of requiring ad-hoc code.
> >>
> >> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> >> Signed-off-by: Simon Goldschmidt <goldsimon at gmx.de>
> >> ---
> > [...]
> >> @@ -22,12 +23,29 @@ static int cadence_spi_write_speed(struct udevice
> *bus, uint hz)
> >>  {
> >>      struct cadence_spi_platdata *plat = bus->platdata;
> >>      struct cadence_spi_priv *priv = dev_get_priv(bus);
> >> +    unsigned int ref_clk_hz;
> >> +    struct clk clk;
> >> +    int ret;
> >> +
> >> +    ret = clk_get_by_index(bus, 0, &clk);
> >> +    if (ret) {
> >> +#ifdef CONFIG_CQSPI_REF_CLK
>
> We also could get rid of CONFIG_CQSPI_REF_CLK altogether. Instead pass
> frequency from DT or platdata using "clock-frequency" property like
> serial drivers do, assuming all platforms now use DT or platdata (all TI
> platforms using this driver support DT).
> But that can be done in a separate patch series...
>

My next step for socfpga is to provide a DM_CLK driver, so that would
remove the need for this define altogether (for that platform).

Regards,
Simon


>
> >> +            ref_clk_hz = CONFIG_CQSPI_REF_CLK;
> >> +#else
> >> +            return ret;
> >> +#endif
> >> +    } else {
> >> +            ref_clk_hz = clk_get_rate(&clk);
> >> +            clk_free(&clk);
> >> +            if (IS_ERR_VALUE(ref_clk_hz))
> >> +                    return ref_clk_hz;
> >> +    }
> >>
> [...]
>
> --
> Regards
> Vignesh
>