[U-Boot] [PATCH v6 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code

[Simon Goldschmidt]

Am 08.11.2019 um 05:11 schrieb Ley Foon Tan:
> Move Stratix10 and Agilex clock manager common code to new header file.
> 
> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>

Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>

> 
> ---
> v6:
> - Move #include <asm/arch/clock_manager_soc64.h> to top of header file.
> 
> v5:
> - Revert CLKMGR_INTOSC_HZ to 460MHz.
> ---
>   .../include/mach/clock_manager_s10.h          | 16 +++----------
>   .../include/mach/clock_manager_soc64.h        | 23 +++++++++++++++++++
>   2 files changed, 26 insertions(+), 13 deletions(-)
>   create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> index 13eb23569c..e710aa2f94 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> @@ -1,12 +1,14 @@
>   /* SPDX-License-Identifier: GPL-2.0
>    *
> - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
>    *
>    */
>   
>   #ifndef	_CLOCK_MANAGER_S10_
>   #define	_CLOCK_MANAGER_S10_
>   
> +#include <asm/arch/clock_manager_soc64.h>
> +
>   /* Clock speed accessors */
>   unsigned long cm_get_mpu_clk_hz(void);
>   unsigned long cm_get_sdram_clk_hz(void);
> @@ -14,18 +16,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
>   unsigned int cm_get_mmc_controller_clk_hz(void);
>   unsigned int cm_get_qspi_controller_clk_hz(void);
>   unsigned int cm_get_spi_controller_clk_hz(void);
> -const unsigned int cm_get_osc_clk_hz(void);
> -const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> -const unsigned int cm_get_intosc_clk_hz(void);
> -const unsigned int cm_get_fpga_clk_hz(void);
> -
> -#define CLKMGR_EOSC1_HZ		25000000
> -#define CLKMGR_INTOSC_HZ	460000000
> -#define CLKMGR_FPGA_CLK_HZ	50000000
> -
> -/* Clock configuration accessors */
> -const struct cm_config * const cm_get_default_config(void);
>   
>   struct cm_config {
>   	/* main group */
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> new file mode 100644
> index 0000000000..3b4bb62ca5
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#ifndef _CLOCK_MANAGER_SOC64_
> +#define _CLOCK_MANAGER_SOC64_
> +
> +const unsigned int cm_get_osc_clk_hz(void);
> +const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> +const unsigned int cm_get_intosc_clk_hz(void);
> +const unsigned int cm_get_fpga_clk_hz(void);
> +
> +#define CLKMGR_EOSC1_HZ		25000000
> +#define CLKMGR_INTOSC_HZ	460000000
> +#define CLKMGR_FPGA_CLK_HZ	50000000
> +
> +/* Clock configuration accessors */
> +const struct cm_config * const cm_get_default_config(void);
> +
> +#endif /* _CLOCK_MANAGER_SOC64_ */
>