[U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由lists.intricate at gmail.com代发】

[Kever Yang]

Hi Kurt,

On 2019/11/14 上午2:44, Kurt Miller wrote:
> On Tue, 2019-09-17 at 12:02 -0400, Kurt Miller wrote:
>> On Tue, 2019-09-17 at 10:57 +0800, Kever Yang wrote:
>>> Hi Kurt,
>>>
>>>       Could you try with below update:
>>>
>>>
>>> diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
>>> b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
>>> index 4a4414a960..dc9db047cb 100644
>>> --- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
>>> +++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
>>> @@ -13,8 +13,8 @@
>>>                   0x2
>>>                   0x1
>>>                   0x0
>>> -               0xf
>>> -               0xf
>>> +               0x10
>>> +               0x10
>>>                   1
>>>                   0x80241d22
>>>                   0x15050f08
>>> @@ -28,8 +28,8 @@
>>>                   0x2
>>>                   0x1
>>>                   0x0
>>> -               0xf
>>> -               0xf
>>> +               0x10
>>> +               0x10
>>>                   1
>>>                   0x80241d22
>>>                   0x15050f08
>>>
>>> Thanks,
>>> - Kever
>> Hi Kever,
>>
>> Yes, that diff does correct the memory size detection
>> for my board:
>>
>> U-Boot TPL 2019.10-rc3-00332-ga314ec1bfd-dirty (Sep 17 2019 - 11:55:26)
>> con reg
>> cru , cic , grf , sgrf , pmucru , pmu
>> Starting SDRAM initialization...
>> sdram_init: data trained for rank 1, ch 0
>> sdram_init: data trained for rank 1, ch 1
>> Channel 0: LPDDR4, 50MHz
>> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
>> Channel 1: LPDDR4, 50MHz
>> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
>> 256B stride
>> lpddr4_set_ctl: channel 0 training pass
>> lpddr4_set_ctl: channel 1 training pass
>> lpddr4_set_rate: change freq to 400 mhz 0, 1
>> lpddr4_set_ctl: channel 0 training pass
>> lpddr4_set_ctl: channel 1 training pass
>> lpddr4_set_rate: change freq to 800 mhz 1, 0
>> Finish SDRAM initialization...
>> Trying to boot from BOOTROM
>> Returning to boot ROM...
> Hi Kever,
>
> Following up on this issue. I retested 2020.01-rc2 to see if
> memory size detection has been fixed yet. Without your diff above
> applied, 2020.01-rc2 still detects 2G memory instead of 4G:


Could you try with latest u-boot-rockchip?

https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git


Thanks,

- Kever

>
> U-Boot TPL 2020.01-rc2-dirty (Nov 13 2019 - 13:18:40)
> con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000
> cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000, pmu ff310000
> Starting SDRAM initialization...
> sdram_init: data trained for rank 1, ch 0
> sdram_init: data trained for rank 1, ch 1
> Channel 0: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> Channel 1: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> 256B stride
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 400 mhz 0, 1
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 800 mhz 1, 0
> Finish SDRAM initialization...
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> With your diff above applied I get 4G correctly:
>
> U-Boot TPL 2020.01-rc2-dirty (Nov 13 2019 - 13:23:22)
> con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000
> cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000, pmu ff310000
> Starting SDRAM initialization...
> sdram_init: data trained for rank 1, ch 0
> sdram_init: data trained for rank 1, ch 1
> Channel 0: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
> Channel 1: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
> 256B stride
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 400 mhz 0, 1
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 800 mhz 1, 0
> Finish SDRAM initialization...
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> Regards,
> -Kurt
>