[U-Boot] [PATCH v3 087/108] spi: ich: Add Apollolake support

[Bin Meng]

Hi Simon,

On Mon, Oct 21, 2019 at 11:40 AM Simon Glass <sjg at chromium.org> wrote:
>
> Add support for Apollolake to the ICH driver. This involves adjusting the
> mmio address and skipping setting of the bbar.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  drivers/spi/ich.c | 19 ++++++++++++++-----
>  drivers/spi/ich.h |  1 +
>  2 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
> index daa69c25a3a..77ab951edc1 100644
> --- a/drivers/spi/ich.c
> +++ b/drivers/spi/ich.c
> @@ -105,10 +105,12 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
>         const uint32_t bbar_mask = 0x00ffff00;
>         uint32_t ichspi_bbar;
>
> -       minaddr &= bbar_mask;
> -       ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
> -       ichspi_bbar |= minaddr;
> -       ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
> +       if (ctlr->bbar) {
> +               minaddr &= bbar_mask;
> +               ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
> +               ichspi_bbar |= minaddr;
> +               ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
> +       }
>  }
>
>  /* @return 1 if the SPI flash supports the 33MHz speed */
> @@ -748,6 +750,7 @@ static int ich_init_controller(struct udevice *dev,
>                 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
>                 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
>                 ctlr->pr = &ich9_spi->pr[0];
> +       } else if (plat->ich_version == ICHV_APL) {
>         } else {
>                 debug("ICH SPI: Unrecognised ICH version %d\n",
>                       plat->ich_version);
> @@ -871,7 +874,12 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev)
>  #if !CONFIG_IS_ENABLED(OF_PLATDATA)
>         plat->ich_version = dev_get_driver_data(dev);
>         plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
> -       pch_get_spi_base(dev->parent, &plat->mmio_base);
> +       if (plat->ich_version == ICHV_APL) {
> +               plat->mmio_base = dm_pci_read_bar32(dev, 0);
> +       } else  {
> +               /* SBASE is similar */
> +               pch_get_spi_base(dev->parent, &plat->mmio_base);

priv->pch, instead of dev->parent?

> +       }
>         plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0);
>  #else
>         plat->ich_version = ICHV_APL;
> @@ -905,6 +913,7 @@ static const struct dm_spi_ops ich_spi_ops = {
>  static const struct udevice_id ich_spi_ids[] = {
>         { .compatible = "intel,ich7-spi", ICHV_7 },
>         { .compatible = "intel,ich9-spi", ICHV_9 },
> +       { .compatible = "intel,fast-spi", ICHV_APL },
>         { }
>  };
>
> diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
> index c7cf37b9321..d7f1ffdf37d 100644
> --- a/drivers/spi/ich.h
> +++ b/drivers/spi/ich.h
> @@ -205,6 +205,7 @@ enum hsfsts_cycle_t {
>  enum ich_version {
>         ICHV_7,
>         ICHV_9,
> +       ICHV_APL,
>  };
>
>  struct ich_spi_priv {
> --

Regards,
Bin