[U-Boot] [RFC PATCH v2 01/18] imx: Add basic support for the NXP IMXRT10xx SoC family
Giulio Benetti
giulio.benetti at benettiengineering.com
Wed Nov 20 17:56:10 UTC 2019
Add i.IMXRT family basic support.
Signed-off-by: Giulio Benetti <giulio.benetti at benettiengineering.com>
---
arch/arm/Kconfig | 10 ++
arch/arm/Makefile | 4 +-
arch/arm/dts/imxrt1050.dtsi | 167 ++++++++++++++++++++
arch/arm/include/asm/arch-imxrt/clock.h | 10 ++
arch/arm/include/asm/arch-imxrt/gpio.h | 19 +++
arch/arm/include/asm/arch-imxrt/imx-regs.h | 20 +++
arch/arm/include/asm/arch-imxrt/imxrt.h | 11 ++
arch/arm/include/asm/arch-imxrt/sys_proto.h | 11 ++
arch/arm/mach-imx/Makefile | 3 +-
arch/arm/mach-imx/imxrt/Kconfig | 6 +
arch/arm/mach-imx/imxrt/Makefile | 7 +
arch/arm/mach-imx/imxrt/soc.c | 35 ++++
12 files changed, 300 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/dts/imxrt1050.dtsi
create mode 100644 arch/arm/include/asm/arch-imxrt/clock.h
create mode 100644 arch/arm/include/asm/arch-imxrt/gpio.h
create mode 100644 arch/arm/include/asm/arch-imxrt/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imxrt/imxrt.h
create mode 100644 arch/arm/include/asm/arch-imxrt/sys_proto.h
create mode 100644 arch/arm/mach-imx/imxrt/Kconfig
create mode 100644 arch/arm/mach-imx/imxrt/Makefile
create mode 100644 arch/arm/mach-imx/imxrt/soc.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f96841c777..24c6a6dbbf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -797,6 +797,14 @@ config ARCH_IMX8M
select SUPPORT_SPL
imply CMD_DM
+config ARCH_IMXRT
+ bool "NXP i.MXRT platform"
+ select CPU_V7M
+ select DM
+ select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM926EJS
@@ -1720,6 +1728,8 @@ source "arch/arm/mach-imx/imx8/Kconfig"
source "arch/arm/mach-imx/imx8m/Kconfig"
+source "arch/arm/mach-imx/imxrt/Kconfig"
+
source "arch/arm/mach-imx/mxs/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5384981c17..5dd9f5b1f6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -104,11 +104,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
libs-y += arch/arm/mach-imx/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
libs-y += arch/arm/mach-imx/
endif
endif
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
new file mode 100644
index 0000000000..cc65c69f83
--- /dev/null
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti at benettiengineering.com>
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/memory/imxrt-sdram.h>
+
+/ {
+ aliases {
+ display0 = &lcdif;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ mmc0 = &usdhc1;
+ serial0 = &lpuart1;
+ };
+
+ clocks {
+ u-boot,dm-spl;
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ ckih1 {
+ compatible = "fsl,imx-ckih1", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ osc {
+ u-boot,dm-spl;
+ compatible = "fsl,imx-osc", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ semc: semc at 402f0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-semc";
+ reg = <0x402f0000 0x4000>;
+ clocks = <&clks IMXRT_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ lpuart1: serial at 40184000 {
+ compatible = "fsl,imxrt-lpuart";
+ reg = <0x40184000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT_CLK_LPUART1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc at 401f8000 {
+ compatible = "fsl,imxrt-iomuxc";
+ reg = <0x401f8000 0x4000>;
+ fsl,mux_mask = <0x7>;
+ };
+
+ clks: ccm at 400fc000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-ccm";
+ reg = <0x400fc000 0x4000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+
+ usdhc1: usdhc at 402c0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-usdhc";
+ reg = <0x402c0000 0x10000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT_CLK_USDHC1>;
+ clock-names = "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio at 401b8000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401b8000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 401bc000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401bc000 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 401c0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401c0000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 401c4000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401c4000 0x4000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio at 400c0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x400c0000 0x4000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ lcdif: lcdif at 402B8000 {
+ compatible = "fsl,imxrt-lcdif";
+ reg = <0x402B8000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT_CLK_LCDIF>;
+ clock-names = "per";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/include/asm/arch-imxrt/clock.h b/arch/arm/include/asm/arch-imxrt/clock.h
new file mode 100644
index 0000000000..7409028b9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/clock.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti at benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-imxrt/gpio.h b/arch/arm/include/asm/arch-imxrt/gpio.h
new file mode 100644
index 0000000000..da31a7438a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/gpio.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti at benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+ u32 gpio_dr; /* data */
+ u32 gpio_dir; /* direction */
+ u32 gpio_psr; /* pad satus */
+};
+#endif
+
+#endif /* __ASM_ARCH_GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h
new file mode 100644
index 0000000000..d21450cfc6
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti at benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define ANATOP_BASE_ADDR 0x400d8000
+
+#define MXS_LCDIF_BASE 0x402b8000
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/mach-imx/regs-lcdif.h>
+#endif
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h
new file mode 100644
index 0000000000..1cb2c57d31
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/imxrt.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti at benettiengineering.com>
+ */
+
+#ifndef _ASM_ARCH_IMXRT_H
+#define _ASM_ARCH_IMXRT_H
+
+#endif /* _ASM_ARCH_IMXRT_H */
+
diff --git a/arch/arm/include/asm/arch-imxrt/sys_proto.h b/arch/arm/include/asm/arch-imxrt/sys_proto.h
new file mode 100644
index 0000000000..eb878e672e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/sys_proto.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e14713c5c4..a70d51b5cf 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -27,7 +27,7 @@ endif
obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
@@ -226,5 +226,6 @@ obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
+obj-$(CONFIG_ARCH_IMXRT) += imxrt/
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
new file mode 100644
index 0000000000..1da002336b
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -0,0 +1,6 @@
+if ARCH_IMXRT
+
+config SYS_SOC
+ default "imxrt"
+
+endif
diff --git a/arch/arm/mach-imx/imxrt/Makefile b/arch/arm/mach-imx/imxrt/Makefile
new file mode 100644
index 0000000000..9621a8335a
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019
+# Author(s): Giulio Benetti <giulio.benetti at benettiengineering.com>
+#
+
+obj-y := soc.o
diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c
new file mode 100644
index 0000000000..e1eea23035
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/soc.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti at benettiengineering.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+
+int arch_cpu_init(void)
+{
+ int i;
+
+ struct mpu_region_config imxrt1050_region_config[] = {
+ { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+ STRONG_ORDER, REGION_4GB },
+ { PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, (ffs(PHYS_SDRAM_SIZE) - 2) },
+ { DMAMEM_BASE,
+ REGION_2, XN_DIS, PRIV_RW_USR_RW,
+ STRONG_ORDER, (ffs(DMAMEM_SZ_ALL) - 2) },
+ };
+
+ /*
+ * Configure the memory protection unit (MPU) to allow full access to
+ * the whole 4GB address space.
+ */
+ disable_mpu();
+ for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
+ mpu_config(&imxrt1050_region_config[i]);
+ enable_mpu();
+
+ return 0;
+}
--
2.20.1
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