[U-Boot] [PATCH v4 055/100] x86: Update .dtsi file for FSP2

[Simon Glass]

Include the IFWI section and the FSP-M binary. The FSP-T binary is not
currently used, as CAR is set up manually.

Also drop the FSP binary as this relates only to FSP1.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v4: None
Changes in v3:
- Add FSP-S and VBT also
- Drop VBT as we already have it elsewhere

Changes in v2: None

 arch/x86/dts/u-boot.dtsi | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 850fe3ac11..14e3c13072 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -100,12 +100,42 @@
 		offset = <CONFIG_X86_MRC_ADDR>;
 	};
 #endif
-#ifdef CONFIG_HAVE_FSP
+#ifdef CONFIG_FSP_VERSION1
 	intel-fsp {
 		filename = CONFIG_FSP_FILE;
 		offset = <CONFIG_FSP_ADDR>;
 	};
 #endif
+#ifdef CONFIG_FSP_VERSION2
+	intel-descriptor {
+		filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+	};
+	intel-ifwi {
+		filename = CONFIG_IFWI_INPUT_FILE;
+		convert-fit;
+
+		section {
+			size = <0x8000>;
+			ifwi-replace;
+			ifwi-subpart = "IBBP";
+			ifwi-entry = "IBBL";
+			u-boot-tpl {
+			};
+			x86-start16-tpl {
+				offset = <0x7800>;
+			};
+			x86-reset16-tpl {
+				offset = <0x7ff0>;
+			};
+		};
+	};
+	intel-fsp-m {
+		filename = CONFIG_FSP_FILE_M;
+	};
+	intel-fsp-s {
+		filename = CONFIG_FSP_FILE_S;
+	};
+#endif
 #ifdef CONFIG_HAVE_CMC
 	intel-cmc {
 		filename = CONFIG_CMC_FILE;
-- 
2.24.0.432.g9d3f5f5b63-goog