[U-Boot] [PATCH v5 053/101] x86: Disable microcode section for FSP2

Simon Glass sjg at chromium.org
Mon Nov 25 04:10:03 UTC 2019


At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.

Signed-off-by: Simon Glass <sjg at chromium.org>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Drop unnecessary #else part of CONFIG_HAVE_MICROCODE

Changes in v2: None

 arch/x86/Kconfig         | 4 ++++
 arch/x86/dts/u-boot.dtsi | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 3dde26ca93..a1c5f5526c 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -588,6 +588,10 @@ config HAVE_REFCODE
           broadwell) U-Boot will be missing some critical setup steps.
           Various peripherals may fail to work.
 
+config HAVE_MICROCODE
+	bool
+	default y if !FSP_VERSION2
+
 config SMP
 	bool "Enable Symmetric Multiprocessing"
 	default n
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 33441c7c80..850fe3ac11 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -37,11 +37,13 @@
 	};
 #endif
 #ifdef CONFIG_TPL
+#ifdef CONFIG_HAVE_MICROCODE
 	u-boot-tpl-with-ucode-ptr {
 		offset = <CONFIG_TPL_TEXT_BASE>;
 	};
 	u-boot-tpl-dtb {
 	};
+#endif
 	u-boot-spl {
 		offset = <CONFIG_SPL_TEXT_BASE>;
 	};
@@ -77,11 +79,16 @@
 		offset = <CONFIG_SYS_TEXT_BASE>;
 	};
 #endif
+#ifdef CONFIG_HAVE_MICROCODE
 	u-boot-dtb-with-ucode {
 	};
 	u-boot-ucode {
 		align = <16>;
 	};
+#else
+	u-boot-dtb {
+	};
+#endif
 #ifdef CONFIG_HAVE_X86_FIT
 	intel-fit {
 	};
-- 
2.24.0.432.g9d3f5f5b63-goog



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