[U-Boot] [PATCH] ddr: fsl: Impl. Erratum A008109

[Joakim Tjernlund]

On Wed, 2019-11-20 at 17:07 +0100, Joakim Tjernlund wrote:
> Impl. erratum as descibed in errata doc.
> Enable A008109 for T1040 and T1024
> 
> Signed-off-by: Joakim Tjernlund <joakim.tjernlund at infinera.com>
> ---
>  arch/powerpc/cpu/mpc85xx/Kconfig | 2 ++
>  drivers/ddr/fsl/Kconfig          | 3 +++
>  drivers/ddr/fsl/ctrl_regs.c      | 6 ++++++
>  3 files changed, 11 insertions(+)
> 
> diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
> index 8cc82f80b4..6caf5c8389 100644
> --- a/arch/powerpc/cpu/mpc85xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc85xx/Kconfig
> @@ -1038,6 +1038,7 @@ config ARCH_T1040
>  	select SYS_FSL_DDR_VER_50
>  	select SYS_FSL_ERRATUM_A008044
>  	select SYS_FSL_ERRATUM_A008378
> +	select SYS_FSL_ERRATUM_A008109
>  	select SYS_FSL_ERRATUM_A009663
>  	select SYS_FSL_ERRATUM_A009942
>  	select SYS_FSL_ERRATUM_ESDHC111
> @@ -1061,6 +1062,7 @@ config ARCH_T1042
>  	select SYS_FSL_DDR_VER_50
>  	select SYS_FSL_ERRATUM_A008044
>  	select SYS_FSL_ERRATUM_A008378
> +	select SYS_FSL_ERRATUM_A008109
>  	select SYS_FSL_ERRATUM_A009663
>  	select SYS_FSL_ERRATUM_A009942
>  	select SYS_FSL_ERRATUM_ESDHC111
> diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
> index 1b73df82de..f75d97b15c 100644
> --- a/drivers/ddr/fsl/Kconfig
> +++ b/drivers/ddr/fsl/Kconfig
> @@ -151,6 +151,9 @@ endmenu
>  config SYS_FSL_ERRATUM_A008378
>  	bool
>  
> +config SYS_FSL_ERRATUM_A008109
> +	bool
> +
>  config SYS_FSL_ERRATUM_A008511
>  	bool
>  
> diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
> index 98ccbb70de..d467160d0c 100644
> --- a/drivers/ddr/fsl/ctrl_regs.c
> +++ b/drivers/ddr/fsl/ctrl_regs.c
> @@ -2626,6 +2626,12 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
>  	}
>  #endif
>  
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A008109
> +	ddr->ddr_sdram_cfg_2 = ddr_in32(&ddr->ddr_sdram_cfg_2) | 0x800; /* DDR_SLOW */
> +	ddr->debug[18] = ddr_in32(&ddrc->debug[18]) | 0x2;
> +	ddr->debug[28] = 0x30000000;
> +#endif
> +

I just noticed something odd(buggy?). Each errata reads from DDR controller bug saves the new
value in a RAM variable(ddr->debug[X]) but does not write values back to HW.

As several erratas update the same register, this looses the previous data.
Also, are theses errtas/debug stateless? Now the code tries gather all writes into a RAM variable and
write the total change in one go later on, this will only work if all errata fixes are stateless.

>  #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
>  	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
>  	ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);