[U-Boot] [PATCH 1/2] arm: rockchip: rk3308: Initialize the iomux configuration

[Kever Yang]

On 2019/11/26 上午9:06, David Wu wrote:
> When we want to use plus iomux feature, we need to enable
> them at spl.
>
> Signed-off-by: David Wu <david.wu at rock-chips.com>
> ---
>   arch/arm/mach-rockchip/rk3308/rk3308.c | 33 ++++++++++++++++++++++++++
>   1 file changed, 33 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c
> index f27f9e8c0b..bd99899094 100644
> --- a/arch/arm/mach-rockchip/rk3308/rk3308.c
> +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
> @@ -72,6 +72,11 @@ enum {
>   	UART2_IO_SEL_M1,
>   	UART2_IO_SEL_USB,
>   
> +	GPIO2C0_SEL_SRC_CTRL_SHIFT	= 11,
> +	GPIO2C0_SEL_SRC_CTRL_MASK	= BIT(11),
> +	GPIO2C0_SEL_SRC_CTRL_IOMUX	= 0,
> +	GPIO2C0_SEL_SRC_CTRL_SEL_PLUS,
> +
>   	GPIO3B3_SEL_SRC_CTRL_SHIFT	= 7,
>   	GPIO3B3_SEL_SRC_CTRL_MASK	= BIT(7),
>   	GPIO3B3_SEL_SRC_CTRL_IOMUX	= 0,
> @@ -97,6 +102,18 @@ enum {
>   	GPIO3B2_SEL_PLUS_EMMC_RSTN,
>   	GPIO3B2_SEL_PLUS_SPI1_MISO,
>   	GPIO3B2_SEL_PLUS_LCDC_D22_M1,
> +
> +	I2C3_IOFUNC_SRC_CTRL_SHIFT	= 10,
> +	I2C3_IOFUNC_SRC_CTRL_MASK	= BIT(10),
> +	I2C3_IOFUNC_SRC_CTRL_SEL_PLUS	= 1,
> +
> +	GPIO2A3_SEL_SRC_CTRL_SHIFT	= 7,
> +	GPIO2A3_SEL_SRC_CTRL_MASK	= BIT(7),
> +	GPIO2A3_SEL_SRC_CTRL_SEL_PLUS	= 1,
> +
> +	GPIO2A2_SEL_SRC_CTRL_SHIFT	= 3,
> +	GPIO2A2_SEL_SRC_CTRL_MASK	= BIT(3),
> +	GPIO2A2_SEL_SRC_CTRL_SEL_PLUS	= 1,
>   };
>   
>   enum {
> @@ -166,10 +183,26 @@ __weak void board_debug_uart_init(void)
>   int arch_cpu_init(void)
>   {
>   	static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
> +	static struct rk3308_grf * const grf = (void *)GRF_BASE;
>   
>   	/* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
>   	rk_clrreg(&sgrf->con_secure0, 0x2b83);
>   
> +
> +	rk_clrsetreg(&grf->soc_con13,

Please add a comment for this two reg write.


Thanks,

- Kever

> +		     I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK |
> +		     GPIO2A2_SEL_SRC_CTRL_MASK,
> +		     I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT |
> +		     GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT |
> +		     GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT);
> +
> +	rk_clrsetreg(&grf->soc_con15,
> +		     GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK |
> +		     GPIO3B2_SEL_SRC_CTRL_MASK,
> +		     GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT |
> +		     GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT |
> +		     GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT);
> +
>   	return 0;
>   }
>   #endif