[U-Boot] [PATCH v2] armv8: fsl-layerscape: LS1044A/1048A: enable Only 1x 10GE port

[Alexandru Marginean]

Hi Pramod,

On 11/25/2019 11:42 AM, Pramod Kumar wrote:
> LS1044A, LS1048A are LS1088A personalities, which support only one
> 1x 10GE port.

There's probably a mix-up, and unfortunately we have an issue in the 
LS1088A reference manual available on the website too.

- LS1088A is documented as 2x 10G, no issue there.

- LS1044A is documented as 1x 10G, no AIOP, no issue there.

- LS1048A I thought is a LS1088A with 4 cores but same DPAA, is it not? 
That's what the numbering scheme should mean at least.
Appending B of the RM has a nice picture of LS1048A which shows 4 cores 
(as expected), 2x 10G ports, AIOP, so the same DPAA as LS1088A.
But the table below mentions '1x 10GE and 8x 1GE'.  One of the two has 
to be wrong.  I place my bet on a copy paste error and on LS1048A having 
2x 10G ports.

- LS1084A, which you did not mention, based on the numbering scheme 
should be a 8 core device with the same DPAA as LS1044A, so 1x 10G. 
Appendix C has a picture that shows a LS1084A device with no AIOP, but 
2x 10G ports.  The table below mentions no AIOP but '2x 10GE and 8x 
1GE'.  I would guess that if LS1044A has just one 10G port then LS1084A 
has just one too.

Can you please double-check and confirm?  It would be nice to open a 
ticket for documentation too, there are definitely some inconsistencies 
there.

And also make sure the patch works for all 4 personalities.

Alex

> MAC1 and MAC2 are associated with 1G SGMII, 2.5G SGMII, and XFI.
> Disable MAC1 to have only one 1x 10GE port for LS1044A, LS1048A.
> 
> Signed-off-by: Pramod Kumar <pramod.kumar_1 at nxp.com>
> ---
> Changes for v2:
>    - incorporated review comment's
> 
>   arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 27 ++++++++++++++++++++--
>   1 file changed, 25 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
> index 8e8b45a..7b465e1 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
> @@ -1,10 +1,12 @@
>   // SPDX-License-Identifier: GPL-2.0+
>   /*
> - * Copyright 2017 NXP
> + * Copyright 2017-2019 NXP
>    */
>   
>   #include <common.h>
>   #include <asm/arch/fsl_serdes.h>
> +#include <asm/arch/soc.h>
> +#include <asm/io.h>
>   
>   struct serdes_config {
>   	u8 ip_protocol;
> @@ -32,6 +34,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
>   	{0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },
>   		{}
>   };
> + >   static struct serdes_config serdes2_cfg_tbl[] = {
>   	/* SerDes 2 */
>   	{0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },
> @@ -48,6 +51,19 @@ static struct serdes_config *serdes_cfg_tbl[] = {
>   	serdes2_cfg_tbl,
>   };
>   
> +bool soc_has_mac1(void)
> +{
> +	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> +	unsigned int  svr, ver;
> +
> +	svr = gur_in32(&gur->svr);
> +	ver = SVR_SOC_VER(svr);
> +	if (ver == SVR_LS1088A)
> +		return true;
> +	else
> +		return false;
> +}
> +
>   int serdes_get_number(int serdes, int cfg)
>   {
>   	struct serdes_config *ptr;
> @@ -87,7 +103,14 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
>   
>   	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
>   		return 0;
> -
> +	/*
> +	 * LS1044A/1048A  support only one XFI port
> +	 * Disable MAC1 for LS1044A/1048A
> +	 */
> +	if (!serdes && lane == 2) {
> +		if (!soc_has_mac1())
> +			return 0;
> +	}
>   	ptr = serdes_cfg_tbl[serdes];
>   	while (ptr->ip_protocol) {
>   		if (ptr->ip_protocol == cfg)
>