[U-Boot] [PATCH v8 17/19] arm: dts: agilex: Add base dtsi and devkit dts
Simon Goldschmidt
simon.k.r.goldschmidt at gmail.com
Thu Nov 28 07:28:33 UTC 2019
On Thu, Nov 28, 2019 at 8:22 AM Ley Foon Tan <lftan.linux at gmail.com> wrote:
>
> On Wed, Nov 27, 2019 at 6:24 PM Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com> wrote:
> >
> > On Wed, Nov 27, 2019 at 8:56 AM Ley Foon Tan <ley.foon.tan at intel.com> wrote:
> > >
> > > Add device tree files for Agilex SoC platform.
> > >
> > > socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains
> > > Uboot specific DT properties.
> > >
> > > socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux
> > > (kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc)
> > >
> > > Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
> > >
> > > ---
> > > v8:
> > > - Include socfpga_agilex-u-boot.dtsi in socfpga_agilex_socdk-u-boot.dtsi,
> > > instead of include it in socfpga_agilex_socdk.dts.
> > >
> > > v7:
> > > - Update socfpga_agilex.dtsi and socfpga_agilex_socdk.dts from Linux.
> > > - Add new socfpga_agilex_socdk-u-boot.dts file for Uboot specific DT
> > > properties.
> > >
> > > v6:
> > > - Use new macro names from agilex-clock.h.
> > >
> > > v5:
> > > - Add CCU DT node.
> > >
> > > v4:
> > > - Add u-boot,dm-pre-reloc to sysmgr node.
> > >
> > > v3:
> > > - Fixed bank 1 memory alias base address to 0x280000000.
> > > - Rename STRATIX10_*_CLK to SOCFPGA_SOC64_*_CLK.
> > > - Include socfpga-soc64-clock.h
> > > - Change to "intel,sdr-ctl-agilex" for SDRAM node.
> > >
> > > v2:
> > > - Add clock property to device node.
> > > - Change memory size to 8GB
> > > - Enable i2c1
> > > ---
> > > arch/arm/dts/Makefile | 1 +
> > > arch/arm/dts/socfpga_agilex-u-boot.dtsi | 96 +++
> > > arch/arm/dts/socfpga_agilex.dtsi | 622 ++++++++++++++++++
> > > arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 39 ++
> > > arch/arm/dts/socfpga_agilex_socdk.dts | 141 ++++
> > > 5 files changed, 899 insertions(+)
> > > create mode 100644 arch/arm/dts/socfpga_agilex-u-boot.dtsi
> > > create mode 100644 arch/arm/dts/socfpga_agilex.dtsi
> > > create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> > > create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts
> > >
> > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > > index d8846df1bd..e76f7c1407 100644
> > > --- a/arch/arm/dts/Makefile
> > > +++ b/arch/arm/dts/Makefile
> > > @@ -328,6 +328,7 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
> > > dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
> > >
> > > dtb-$(CONFIG_ARCH_SOCFPGA) += \
> > > + socfpga_agilex_socdk.dtb \
> > > socfpga_arria5_socdk.dtb \
> > > socfpga_arria10_socdk_sdmmc.dtb \
> > > socfpga_cyclone5_mcvevk.dtb \
> > > diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
> > > new file mode 100644
> > > index 0000000000..f0528a9ad9
> > > --- /dev/null
> > > +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
> > > @@ -0,0 +1,96 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * U-Boot additions
> > > + *
> > > + * Copyright (C) 2019 Intel Corporation <www.intel.com>
> > > + */
> > > +
> > > +/{
> > > + memory {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + u-boot,dm-pre-reloc;
> > > + };
> > > +
> > > + soc {
> > > + u-boot,dm-pre-reloc;
> > > +
> > > + ccu: cache-controller at f7000000 {
> > > + compatible = "arteris,ncore-ccu";
> > > + reg = <0xf7000000 0x100900>;
> > > + u-boot,dm-pre-reloc;
> > > + };
> > > + };
> > > +};
> > > +
> > > +&clkmgr {
> > > + u-boot,dm-pre-reloc;
> > > +};
> > > +
> > > +&gmac1 {
> > > + altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> > > +};
> > > +
> > > +&gmac2 {
> > > + altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
> > > +};
> > > +
> > > +&i2c0 {
> > > + reset-names = "i2c";
> > > +};
> > > +
> > > +&i2c1 {
> > > + reset-names = "i2c";
> > > +};
> > > +
> > > +&i2c2 {
> > > + reset-names = "i2c";
> > > +};
> > > +
> > > +&i2c3 {
> > > + reset-names = "i2c";
> > > +};
> > > +
> > > +&mmc {
> > > + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
> > > +};
> > > +
> > > +&porta {
> > > + bank-name = "porta";
> > > +};
> > > +
> > > +&portb {
> > > + bank-name = "portb";
> > > +};
> > > +
> > > +&qspi {
> > > + u-boot,dm-pre-reloc;
> > > +};
> > > +
> > > +&rst {
> > > + compatible = "altr,rst-mgr";
> >
> > This and other compatible-changing lines in this file should be synced to the
> > correct string in all DTs, so please fix this in the upstream Linux DTs.
> Linux uses "altr,rst-mgr" for Gen5 and Arria10,
> "altr,stratix10-rst-mgr" for S10 and Agilex.
> But, Uboot uses "altr,rst-mgr" for all Gen5/Arria10/S10/Agilex platforms.
What prevents you from fixing the Linux drivers to use
"altr,stratix10-rst-mgr", too?
A devicetree should describe the hardware in a generic, OS-agnostic way
as much as possible.
>
> >
> > > + altr,modrst-offset = <0x20>;
> > > + u-boot,dm-pre-reloc;
> > > +};
> > > +
> > > +&sdr {
> > > + compatible = "intel,sdr-ctl-agilex";
> >
> > See above.
> Linux doesn't have DDR device tree node. DDR driver is only needed in Uboot.
That's not the point. As written above, a devicetree describes hardware. The
fact that Linux does not use this piece of hardware doesn't mean it must
be removed from the dts in the Linux sources.
>
> >
> > > + reg = <0xf8000400 0x80>,
> > > + <0xf8010000 0x190>,
> > > + <0xf8011000 0x500>;
> > > + resets = <&rst DDRSCH_RESET>;
> > > + u-boot,dm-pre-reloc;
> > > +};
> > > +
> > > +&sysmgr {
> > > + compatible = "altr,sys-mgr", "syscon";
> >
> > See above.
> Linux dts just removed "syscon" recently. But, Uboot needs it.
Hmm, can we fix the sysmgr driver to behave as syscon? Than we
could remove this for U-Boot, too.
Regards,
Simon
>
> Regards
> Ley Foon
>
> >
> > Ultimately, you should onle need 'u-boot,dm-pre-reloc' tags in this file
> > and probably some boot source defititions.
> >
> > However, until that is done, it's probably ok to have this here, so:
> > Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> >
> > > + u-boot,dm-pre-reloc;
> > > +};
> > > +
> > > +&uart0 {
> > > + u-boot,dm-pre-reloc;
> > > +};
> > > +
> > > +&watchdog0 {
> > > + u-boot,dm-pre-reloc;
> > > +};
> > > diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi
> > > new file mode 100644
> > > index 0000000000..179b4d5591
> > > --- /dev/null
> > > +++ b/arch/arm/dts/socfpga_agilex.dtsi
> > > @@ -0,0 +1,622 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright (C) 2019, Intel Corporation
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/clock/agilex-clock.h>
> > > +
> > > +/ {
> > > + compatible = "intel,socfpga-agilex";
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > +
> > > + reserved-memory {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + ranges;
> > > +
> > > + service_reserved: svcbuffer at 0 {
> > > + compatible = "shared-dma-pool";
> > > + reg = <0x0 0x0 0x0 0x1000000>;
> > > + alignment = <0x1000>;
> > > + no-map;
> > > + };
> > > + };
> > > +
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + cpu0: cpu at 0 {
> > > + compatible = "arm,cortex-a53";
> > > + device_type = "cpu";
> > > + enable-method = "psci";
> > > + reg = <0x0>;
> > > + };
> > > +
> > > + cpu1: cpu at 1 {
> > > + compatible = "arm,cortex-a53";
> > > + device_type = "cpu";
> > > + enable-method = "psci";
> > > + reg = <0x1>;
> > > + };
> > > +
> > > + cpu2: cpu at 2 {
> > > + compatible = "arm,cortex-a53";
> > > + device_type = "cpu";
> > > + enable-method = "psci";
> > > + reg = <0x2>;
> > > + };
> > > +
> > > + cpu3: cpu at 3 {
> > > + compatible = "arm,cortex-a53";
> > > + device_type = "cpu";
> > > + enable-method = "psci";
> > > + reg = <0x3>;
> > > + };
> > > + };
> > > +
> > > + pmu {
> > > + compatible = "arm,armv8-pmuv3";
> > > + interrupts = <0 170 4>,
> > > + <0 171 4>,
> > > + <0 172 4>,
> > > + <0 173 4>;
> > > + interrupt-affinity = <&cpu0>,
> > > + <&cpu1>,
> > > + <&cpu2>,
> > > + <&cpu3>;
> > > + interrupt-parent = <&intc>;
> > > + };
> > > +
> > > + psci {
> > > + compatible = "arm,psci-0.2";
> > > + method = "smc";
> > > + };
> > > +
> > > + intc: intc at fffc1000 {
> > > + compatible = "arm,gic-400", "arm,cortex-a15-gic";
> > > + #interrupt-cells = <3>;
> > > + interrupt-controller;
> > > + reg = <0x0 0xfffc1000 0x0 0x1000>,
> > > + <0x0 0xfffc2000 0x0 0x2000>,
> > > + <0x0 0xfffc4000 0x0 0x2000>,
> > > + <0x0 0xfffc6000 0x0 0x2000>;
> > > + };
> > > +
> > > + soc {
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + compatible = "simple-bus";
> > > + device_type = "soc";
> > > + interrupt-parent = <&intc>;
> > > + ranges = <0 0 0 0xffffffff>;
> > > +
> > > + base_fpga_region {
> > > + #address-cells = <0x1>;
> > > + #size-cells = <0x1>;
> > > + compatible = "fpga-region";
> > > + fpga-mgr = <&fpga_mgr>;
> > > + };
> > > +
> > > + clkmgr: clock-controller at ffd10000 {
> > > + compatible = "intel,agilex-clkmgr";
> > > + reg = <0xffd10000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + clocks {
> > > + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
> > > + #clock-cells = <0>;
> > > + compatible = "fixed-clock";
> > > + };
> > > +
> > > + cb_intosc_ls_clk: cb-intosc-ls-clk {
> > > + #clock-cells = <0>;
> > > + compatible = "fixed-clock";
> > > + };
> > > +
> > > + f2s_free_clk: f2s-free-clk {
> > > + #clock-cells = <0>;
> > > + compatible = "fixed-clock";
> > > + };
> > > +
> > > + osc1: osc1 {
> > > + #clock-cells = <0>;
> > > + compatible = "fixed-clock";
> > > + };
> > > +
> > > + qspi_clk: qspi-clk {
> > > + #clock-cells = <0>;
> > > + compatible = "fixed-clock";
> > > + clock-frequency = <200000000>;
> > > + };
> > > + };
> > > + gmac0: ethernet at ff800000 {
> > > + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> > > + reg = <0xff800000 0x2000>;
> > > + interrupts = <0 90 4>;
> > > + interrupt-names = "macirq";
> > > + mac-address = [00 00 00 00 00 00];
> > > + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
> > > + reset-names = "stmmaceth", "stmmaceth-ocp";
> > > + tx-fifo-depth = <16384>;
> > > + rx-fifo-depth = <16384>;
> > > + snps,multicast-filter-bins = <256>;
> > > + iommus = <&smmu 1>;
> > > + altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> > > + clocks = <&clkmgr AGILEX_EMAC0_CLK>;
> > > + clock-names = "stmmaceth";
> > > + status = "disabled";
> > > + };
> > > +
> > > + gmac1: ethernet at ff802000 {
> > > + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> > > + reg = <0xff802000 0x2000>;
> > > + interrupts = <0 91 4>;
> > > + interrupt-names = "macirq";
> > > + mac-address = [00 00 00 00 00 00];
> > > + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
> > > + reset-names = "stmmaceth", "stmmaceth-ocp";
> > > + tx-fifo-depth = <16384>;
> > > + rx-fifo-depth = <16384>;
> > > + snps,multicast-filter-bins = <256>;
> > > + iommus = <&smmu 2>;
> > > + altr,sysmgr-syscon = <&sysmgr 0x48 8>;
> > > + clocks = <&clkmgr AGILEX_EMAC1_CLK>;
> > > + clock-names = "stmmaceth";
> > > + status = "disabled";
> > > + };
> > > +
> > > + gmac2: ethernet at ff804000 {
> > > + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> > > + reg = <0xff804000 0x2000>;
> > > + interrupts = <0 92 4>;
> > > + interrupt-names = "macirq";
> > > + mac-address = [00 00 00 00 00 00];
> > > + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
> > > + reset-names = "stmmaceth", "stmmaceth-ocp";
> > > + tx-fifo-depth = <16384>;
> > > + rx-fifo-depth = <16384>;
> > > + snps,multicast-filter-bins = <256>;
> > > + iommus = <&smmu 3>;
> > > + altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
> > > + clocks = <&clkmgr AGILEX_EMAC2_CLK>;
> > > + clock-names = "stmmaceth";
> > > + status = "disabled";
> > > + };
> > > +
> > > + gpio0: gpio at ffc03200 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "snps,dw-apb-gpio";
> > > + reg = <0xffc03200 0x100>;
> > > + resets = <&rst GPIO0_RESET>;
> > > + status = "disabled";
> > > +
> > > + porta: gpio-controller at 0 {
> > > + compatible = "snps,dw-apb-gpio-port";
> > > + gpio-controller;
> > > + #gpio-cells = <2>;
> > > + snps,nr-gpios = <24>;
> > > + reg = <0>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <2>;
> > > + interrupts = <0 110 4>;
> > > + };
> > > + };
> > > +
> > > + gpio1: gpio at ffc03300 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "snps,dw-apb-gpio";
> > > + reg = <0xffc03300 0x100>;
> > > + resets = <&rst GPIO1_RESET>;
> > > + status = "disabled";
> > > +
> > > + portb: gpio-controller at 0 {
> > > + compatible = "snps,dw-apb-gpio-port";
> > > + gpio-controller;
> > > + #gpio-cells = <2>;
> > > + snps,nr-gpios = <24>;
> > > + reg = <0>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <2>;
> > > + interrupts = <0 111 4>;
> > > + };
> > > + };
> > > +
> > > + i2c0: i2c at ffc02800 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "snps,designware-i2c";
> > > + reg = <0xffc02800 0x100>;
> > > + interrupts = <0 103 4>;
> > > + resets = <&rst I2C0_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c1: i2c at ffc02900 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "snps,designware-i2c";
> > > + reg = <0xffc02900 0x100>;
> > > + interrupts = <0 104 4>;
> > > + resets = <&rst I2C1_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c2: i2c at ffc02a00 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "snps,designware-i2c";
> > > + reg = <0xffc02a00 0x100>;
> > > + interrupts = <0 105 4>;
> > > + resets = <&rst I2C2_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c3: i2c at ffc02b00 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "snps,designware-i2c";
> > > + reg = <0xffc02b00 0x100>;
> > > + interrupts = <0 106 4>;
> > > + resets = <&rst I2C3_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c4: i2c at ffc02c00 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "snps,designware-i2c";
> > > + reg = <0xffc02c00 0x100>;
> > > + interrupts = <0 107 4>;
> > > + resets = <&rst I2C4_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + mmc: dwmmc0 at ff808000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "altr,socfpga-dw-mshc";
> > > + reg = <0xff808000 0x1000>;
> > > + interrupts = <0 96 4>;
> > > + fifo-depth = <0x400>;
> > > + resets = <&rst SDMMC_RESET>;
> > > + reset-names = "reset";
> > > + clocks = <&clkmgr AGILEX_L4_MP_CLK>,
> > > + <&clkmgr AGILEX_SDMMC_CLK>;
> > > + clock-names = "biu", "ciu";
> > > + iommus = <&smmu 5>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + nand: nand at ffb90000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "altr,socfpga-denali-nand";
> > > + reg = <0xffb90000 0x10000>,
> > > + <0xffb80000 0x1000>;
> > > + reg-names = "nand_data", "denali_reg";
> > > + interrupts = <0 97 4>;
> > > + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + ocram: sram at ffe00000 {
> > > + compatible = "mmio-sram";
> > > + reg = <0xffe00000 0x40000>;
> > > + };
> > > +
> > > + pdma: pdma at ffda0000 {
> > > + compatible = "arm,pl330", "arm,primecell";
> > > + reg = <0xffda0000 0x1000>;
> > > + interrupts = <0 81 4>,
> > > + <0 82 4>,
> > > + <0 83 4>,
> > > + <0 84 4>,
> > > + <0 85 4>,
> > > + <0 86 4>,
> > > + <0 87 4>,
> > > + <0 88 4>,
> > > + <0 89 4>;
> > > + #dma-cells = <1>;
> > > + #dma-channels = <8>;
> > > + #dma-requests = <32>;
> > > + resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
> > > + reset-names = "dma", "dma-ocp";
> > > + clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
> > > + clock-names = "apb_pclk";
> > > + };
> > > +
> > > + rst: rstmgr at ffd11000 {
> > > + #reset-cells = <1>;
> > > + compatible = "altr,stratix10-rst-mgr";
> > > + reg = <0xffd11000 0x100>;
> > > + };
> > > +
> > > + smmu: iommu at fa000000 {
> > > + compatible = "arm,mmu-500", "arm,smmu-v2";
> > > + reg = <0xfa000000 0x40000>;
> > > + #global-interrupts = <2>;
> > > + #iommu-cells = <1>;
> > > + interrupt-parent = <&intc>;
> > > + interrupts = <0 128 4>, /* Global Secure Fault */
> > > + <0 129 4>, /* Global Non-secure Fault */
> > > + /* Non-secure Context Interrupts (32) */
> > > + <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
> > > + <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
> > > + <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
> > > + <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
> > > + <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
> > > + <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
> > > + <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
> > > + <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
> > > + stream-match-mask = <0x7ff0>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + spi0: spi at ffda4000 {
> > > + compatible = "snps,dw-apb-ssi";
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + reg = <0xffda4000 0x1000>;
> > > + interrupts = <0 99 4>;
> > > + resets = <&rst SPIM0_RESET>;
> > > + reg-io-width = <4>;
> > > + num-cs = <4>;
> > > + clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + spi1: spi at ffda5000 {
> > > + compatible = "snps,dw-apb-ssi";
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + reg = <0xffda5000 0x1000>;
> > > + interrupts = <0 100 4>;
> > > + resets = <&rst SPIM1_RESET>;
> > > + reg-io-width = <4>;
> > > + num-cs = <4>;
> > > + clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + sysmgr: sysmgr at ffd12000 {
> > > + compatible = "altr,sys-mgr-s10","altr,sys-mgr";
> > > + reg = <0xffd12000 0x500>;
> > > + };
> > > +
> > > + /* Local timer */
> > > + timer {
> > > + compatible = "arm,armv8-timer";
> > > + interrupts = <1 13 0xf08>,
> > > + <1 14 0xf08>,
> > > + <1 11 0xf08>,
> > > + <1 10 0xf08>;
> > > + };
> > > +
> > > + timer0: timer0 at ffc03000 {
> > > + compatible = "snps,dw-apb-timer";
> > > + interrupts = <0 113 4>;
> > > + reg = <0xffc03000 0x100>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + clock-names = "timer";
> > > + };
> > > +
> > > + timer1: timer1 at ffc03100 {
> > > + compatible = "snps,dw-apb-timer";
> > > + interrupts = <0 114 4>;
> > > + reg = <0xffc03100 0x100>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + clock-names = "timer";
> > > + };
> > > +
> > > + timer2: timer2 at ffd00000 {
> > > + compatible = "snps,dw-apb-timer";
> > > + interrupts = <0 115 4>;
> > > + reg = <0xffd00000 0x100>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + clock-names = "timer";
> > > + };
> > > +
> > > + timer3: timer3 at ffd00100 {
> > > + compatible = "snps,dw-apb-timer";
> > > + interrupts = <0 116 4>;
> > > + reg = <0xffd00100 0x100>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + clock-names = "timer";
> > > + };
> > > +
> > > + uart0: serial0 at ffc02000 {
> > > + compatible = "snps,dw-apb-uart";
> > > + reg = <0xffc02000 0x100>;
> > > + interrupts = <0 108 4>;
> > > + reg-shift = <2>;
> > > + reg-io-width = <4>;
> > > + resets = <&rst UART0_RESET>;
> > > + status = "disabled";
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + clock-frequency = <100000000>;
> > > + };
> > > +
> > > + uart1: serial1 at ffc02100 {
> > > + compatible = "snps,dw-apb-uart";
> > > + reg = <0xffc02100 0x100>;
> > > + interrupts = <0 109 4>;
> > > + reg-shift = <2>;
> > > + reg-io-width = <4>;
> > > + resets = <&rst UART1_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SP_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usbphy0: usbphy at 0 {
> > > + #phy-cells = <0>;
> > > + compatible = "usb-nop-xceiv";
> > > + status = "okay";
> > > + };
> > > +
> > > + usb0: usb at ffb00000 {
> > > + compatible = "snps,dwc2";
> > > + reg = <0xffb00000 0x40000>;
> > > + interrupts = <0 93 4>;
> > > + phys = <&usbphy0>;
> > > + phy-names = "usb2-phy";
> > > + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
> > > + reset-names = "dwc2", "dwc2-ecc";
> > > + clocks = <&clkmgr AGILEX_USB_CLK>;
> > > + iommus = <&smmu 6>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usb1: usb at ffb40000 {
> > > + compatible = "snps,dwc2";
> > > + reg = <0xffb40000 0x40000>;
> > > + interrupts = <0 94 4>;
> > > + phys = <&usbphy0>;
> > > + phy-names = "usb2-phy";
> > > + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
> > > + reset-names = "dwc2", "dwc2-ecc";
> > > + iommus = <&smmu 7>;
> > > + clocks = <&clkmgr AGILEX_USB_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + watchdog0: watchdog at ffd00200 {
> > > + compatible = "snps,dw-wdt";
> > > + reg = <0xffd00200 0x100>;
> > > + interrupts = <0 117 4>;
> > > + resets = <&rst WATCHDOG0_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + watchdog1: watchdog at ffd00300 {
> > > + compatible = "snps,dw-wdt";
> > > + reg = <0xffd00300 0x100>;
> > > + interrupts = <0 118 4>;
> > > + resets = <&rst WATCHDOG1_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + watchdog2: watchdog at ffd00400 {
> > > + compatible = "snps,dw-wdt";
> > > + reg = <0xffd00400 0x100>;
> > > + interrupts = <0 125 4>;
> > > + resets = <&rst WATCHDOG2_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + watchdog3: watchdog at ffd00500 {
> > > + compatible = "snps,dw-wdt";
> > > + reg = <0xffd00500 0x100>;
> > > + interrupts = <0 126 4>;
> > > + resets = <&rst WATCHDOG3_RESET>;
> > > + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + sdr: sdr at f8011100 {
> > > + compatible = "altr,sdr-ctl", "syscon";
> > > + reg = <0xf8011100 0xc0>;
> > > + };
> > > +
> > > + eccmgr {
> > > + compatible = "altr,socfpga-s10-ecc-manager",
> > > + "altr,socfpga-a10-ecc-manager";
> > > + altr,sysmgr-syscon = <&sysmgr>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + interrupts = <0 15 4>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <2>;
> > > + ranges;
> > > +
> > > + sdramedac {
> > > + compatible = "altr,sdram-edac-s10";
> > > + altr,sdr-syscon = <&sdr>;
> > > + interrupts = <16 4>;
> > > + };
> > > +
> > > + ocram-ecc at ff8cc000 {
> > > + compatible = "altr,socfpga-s10-ocram-ecc",
> > > + "altr,socfpga-a10-ocram-ecc";
> > > + reg = <0xff8cc000 0x100>;
> > > + altr,ecc-parent = <&ocram>;
> > > + interrupts = <1 4>;
> > > + };
> > > +
> > > + usb0-ecc at ff8c4000 {
> > > + compatible = "altr,socfpga-s10-usb-ecc",
> > > + "altr,socfpga-usb-ecc";
> > > + reg = <0xff8c4000 0x100>;
> > > + altr,ecc-parent = <&usb0>;
> > > + interrupts = <2 4>;
> > > + };
> > > +
> > > + emac0-rx-ecc at ff8c0000 {
> > > + compatible = "altr,socfpga-s10-eth-mac-ecc",
> > > + "altr,socfpga-eth-mac-ecc";
> > > + reg = <0xff8c0000 0x100>;
> > > + altr,ecc-parent = <&gmac0>;
> > > + interrupts = <4 4>;
> > > + };
> > > +
> > > + emac0-tx-ecc at ff8c0400 {
> > > + compatible = "altr,socfpga-s10-eth-mac-ecc",
> > > + "altr,socfpga-eth-mac-ecc";
> > > + reg = <0xff8c0400 0x100>;
> > > + altr,ecc-parent = <&gmac0>;
> > > + interrupts = <5 4>;
> > > + };
> > > +
> > > + sdmmca-ecc at ff8c8c00 {
> > > + compatible = "altr,socfpga-s10-sdmmc-ecc",
> > > + "altr,socfpga-sdmmc-ecc";
> > > + reg = <0xff8c8c00 0x100>;
> > > + altr,ecc-parent = <&mmc>;
> > > + interrupts = <14 4>,
> > > + <15 4>;
> > > + };
> > > + };
> > > +
> > > + qspi: spi at ff8d2000 {
> > > + compatible = "cdns,qspi-nor";
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + reg = <0xff8d2000 0x100>,
> > > + <0xff900000 0x100000>;
> > > + interrupts = <0 3 4>;
> > > + cdns,fifo-depth = <128>;
> > > + cdns,fifo-width = <4>;
> > > + cdns,trigger-address = <0x00000000>;
> > > + clocks = <&qspi_clk>;
> > > +
> > > + status = "disabled";
> > > + };
> > > +
> > > + firmware {
> > > + svc {
> > > + compatible = "intel,stratix10-svc";
> > > + method = "smc";
> > > + memory-region = <&service_reserved>;
> > > +
> > > + fpga_mgr: fpga-mgr {
> > > + compatible = "intel,stratix10-soc-fpga-mgr";
> > > + };
> > > + };
> > > + };
> > > + };
> > > +};
> > > diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> > > new file mode 100644
> > > index 0000000000..1908be4b8b
> > > --- /dev/null
> > > +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> > > @@ -0,0 +1,39 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * U-Boot additions
> > > + *
> > > + * Copyright (C) 2019 Intel Corporation <www.intel.com>
> > > + */
> > > +
> > > +#include "socfpga_agilex-u-boot.dtsi"
> > > +
> > > +/{
> > > + aliases {
> > > + spi0 = &qspi;
> > > + i2c0 = &i2c1;
> > > + };
> > > +
> > > + memory {
> > > + /* 8GB */
> > > + reg = <0 0x00000000 0 0x80000000>,
> > > + <2 0x80000000 1 0x80000000>;
> > > + };
> > > +};
> > > +
> > > +&flash0 {
> > > + compatible = "jedec,spi-nor";
> > > + spi-tx-bus-width = <4>;
> > > + spi-rx-bus-width = <4>;
> > > + u-boot,dm-pre-reloc;
> > > +};
> > > +
> > > +&i2c1 {
> > > + status = "okay";
> > > +};
> > > +
> > > +&mmc {
> > > + drvsel = <3>;
> > > + smplsel = <0>;
> > > + u-boot,dm-pre-reloc;
> > > +};
> > > +
> > > diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex_socdk.dts
> > > new file mode 100644
> > > index 0000000000..bcdeecc0e0
> > > --- /dev/null
> > > +++ b/arch/arm/dts/socfpga_agilex_socdk.dts
> > > @@ -0,0 +1,141 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright (C) 2019, Intel Corporation
> > > + */
> > > +#include "socfpga_agilex.dtsi"
> > > +
> > > +/ {
> > > + model = "SoCFPGA Agilex SoCDK";
> > > +
> > > + aliases {
> > > + serial0 = &uart0;
> > > + ethernet0 = &gmac0;
> > > + ethernet1 = &gmac1;
> > > + ethernet2 = &gmac2;
> > > + };
> > > +
> > > + chosen {
> > > + stdout-path = "serial0:115200n8";
> > > + };
> > > +
> > > + leds {
> > > + compatible = "gpio-leds";
> > > + hps0 {
> > > + label = "hps_led0";
> > > + gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
> > > + };
> > > +
> > > + hps1 {
> > > + label = "hps_led1";
> > > + gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
> > > + };
> > > +
> > > + hps2 {
> > > + label = "hps_led2";
> > > + gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
> > > + };
> > > + };
> > > +
> > > + memory {
> > > + device_type = "memory";
> > > + /* We expect the bootloader to fill in the reg */
> > > + reg = <0 0 0 0>;
> > > + };
> > > +
> > > + soc {
> > > + clocks {
> > > + osc1 {
> > > + clock-frequency = <25000000>;
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +&gpio1 {
> > > + status = "okay";
> > > +};
> > > +
> > > +&gmac0 {
> > > + status = "okay";
> > > + phy-mode = "rgmii";
> > > + phy-handle = <&phy0>;
> > > +
> > > + max-frame-size = <9000>;
> > > +
> > > + mdio0 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "snps,dwmac-mdio";
> > > + phy0: ethernet-phy at 0 {
> > > + reg = <4>;
> > > +
> > > + txd0-skew-ps = <0>; /* -420ps */
> > > + txd1-skew-ps = <0>; /* -420ps */
> > > + txd2-skew-ps = <0>; /* -420ps */
> > > + txd3-skew-ps = <0>; /* -420ps */
> > > + rxd0-skew-ps = <420>; /* 0ps */
> > > + rxd1-skew-ps = <420>; /* 0ps */
> > > + rxd2-skew-ps = <420>; /* 0ps */
> > > + rxd3-skew-ps = <420>; /* 0ps */
> > > + txen-skew-ps = <0>; /* -420ps */
> > > + txc-skew-ps = <900>; /* 0ps */
> > > + rxdv-skew-ps = <420>; /* 0ps */
> > > + rxc-skew-ps = <1680>; /* 780ps */
> > > + };
> > > + };
> > > +};
> > > +
> > > +&mmc {
> > > + status = "okay";
> > > + cap-sd-highspeed;
> > > + broken-cd;
> > > + bus-width = <4>;
> > > +};
> > > +
> > > +&uart0 {
> > > + status = "okay";
> > > +};
> > > +
> > > +&usb0 {
> > > + status = "okay";
> > > + disable-over-current;
> > > +};
> > > +
> > > +&watchdog0 {
> > > + status = "okay";
> > > +};
> > > +
> > > +&qspi {
> > > + flash0: flash at 0 {
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + compatible = "mt25qu02g";
> > > + reg = <0>;
> > > + spi-max-frequency = <100000000>;
> > > +
> > > + m25p,fast-read;
> > > + cdns,page-size = <256>;
> > > + cdns,block-size = <16>;
> > > + cdns,read-delay = <1>;
> > > + cdns,tshsl-ns = <50>;
> > > + cdns,tsd2d-ns = <50>;
> > > + cdns,tchsh-ns = <4>;
> > > + cdns,tslch-ns = <4>;
> > > +
> > > + partitions {
> > > + compatible = "fixed-partitions";
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > +
> > > + qspi_boot: partition at 0 {
> > > + label = "Boot and fpga data";
> > > + reg = <0x0 0x034B0000>;
> > > + };
> > > +
> > > + qspi_rootfs: partition at 34B0000 {
> > > + label = "Root Filesystem - JFFS2";
> > > + reg = <0x034B0000 0x0EB50000>;
> > > + };
> > > + };
> > > + };
> > > +};
> > > --
> > > 2.19.0
> > >
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