[U-Boot] [PATCH 079/126] x86: Reduce mrccache record alignment size

[Simon Glass]

Hi Bin,

On Wed, 9 Oct 2019 at 23:09, Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Hi Simon,
>
> On Wed, Sep 25, 2019 at 10:59 PM Simon Glass <sjg at chromium.org> wrote:
> >
> > At present the records are 4KB in size. This is unnecessarily large when
> > the SPI-flash erase size is 256 bytes. Reduce it so it will be more
>
> But this will break for SPI-flash erase size that is not 256 bytes?

The way it works is that it erases the whole region, then fills it up
record by record, then when it gets full, erases it all again. So I
think it is OK.

Regards,
Simon