[U-Boot] [PATCH] ARM: dts: zynq: enablement of coresight topology
Michal Simek
michal.simek at xilinx.com
Thu Oct 24 07:05:28 UTC 2019
Hi Mathieu,
On 23. 10. 19 19:32, Mathieu Poirier wrote:
> Hi Michal,
>
> I was not CC'ed on the original post so I just noticed this today,
> hence the late reply. I don't know if you were looking for feedback
> or already picked up the patch but here it is anyway.
I haven't put the patch to my zynq/dt branch yet. And definitely any
feedback on this is welcome.
>
> On Wed, 9 Oct 2019 at 08:07, Michal Simek <michal.simek at xilinx.com> wrote:
>>
>> From: Zumeng Chen <zumeng.chen at windriver.com>
>>
>> This patch is to build the coresight topology structure of zynq-7000
>> series according to the docs of coresight and userguide of zynq-7000.
>>
>> Signed-off-by: Zumeng Chen <zumeng.chen at windriver.com>
>> Signed-off-by: Quanyang Wang <quanyang.wang at windriver.com>
>> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
>> ---
>>
>> arch/arm/boot/dts/zynq-7000.dtsi | 158 +++++++++++++++++++++++++++++++
>> 1 file changed, 158 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
>> index ca6425ad794c..86430ad76fee 100644
>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>> @@ -59,6 +59,40 @@
>> regulator-always-on;
>> };
>>
>> + replicator {
>> + compatible = "arm,coresight-static-replicator";
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> +
>> + out-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* replicator output ports */
>> + port at 0 {
>> + reg = <0>;
>> + replicator_out_port0: endpoint {
>> + remote-endpoint = <&tpiu_in_port>;
>> + };
>> + };
>> + port at 1 {
>> + reg = <1>;
>> + replicator_out_port1: endpoint {
>> + remote-endpoint = <&etb_in_port>;
>> + };
>> + };
>> + };
>> + in-ports {
>> + /* replicator input port */
>> + port {
>> + replicator_in_port0: endpoint {
>> + slave-mode;
>
> The slave-mode property is no longer required and probably an
> oversight since it doesn't appear elsewhere in this patch.
likely yes. I will remove it.
>
>> + remote-endpoint = <&funnel_out_port>;
>> + };
>> + };
>> + };
>> + };
>> +
>> amba: amba {
>> compatible = "simple-bus";
>> #address-cells = <1>;
>> @@ -365,5 +399,129 @@
>> reg = <0xf8005000 0x1000>;
>> timeout-sec = <10>;
>> };
>> +
>> + etb at f8801000 {
>> + compatible = "arm,coresight-etb10", "arm,primecell";
>> + reg = <0xf8801000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + in-ports {
>> + port {
>> + etb_in_port: endpoint {
>> + remote-endpoint = <&replicator_out_port1>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + tpiu at f8803000 {
>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>> + reg = <0xf8803000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + in-ports {
>> + port {
>> + tpiu_in_port: endpoint {
>> + remote-endpoint = <&replicator_out_port0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel at f8804000 {
>> + compatible = "arm,coresight-static-funnel", "arm,primecell";
>> + reg = <0xf8804000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> +
>> + /* funnel output ports */
>> + out-ports {
>> + port {
>> + funnel_out_port: endpoint {
>> + remote-endpoint =
>> + <&replicator_in_port0>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* funnel input ports */
>> + port at 0 {
>> + reg = <0>;
>> + funnel0_in_port0: endpoint {
>> + remote-endpoint = <&ptm0_out_port>;
>> + };
>> + };
>> +
>> + port at 1 {
>> + reg = <1>;
>> + funnel0_in_port1: endpoint {
>> + remote-endpoint = <&ptm1_out_port>;
>> + };
>> + };
>> +
>> + port at 2 {
>> + reg = <2>;
>> + funnel0_in_port2: endpoint {
>> + };
>> + };
>> +
>> + port at 3 {
>> + reg = <3>;
>> + funnel0_in_port3: endpoint {
>> + remote-endpoint = <&itm_out_port>;
>> + };
>> + };
>> + /* The other input ports are not connect to anything */
>> + };
>> + };
>> +
>> + /* ITM is not supported by kernel, only leave device node here */
>> + itm at f8805000 {
>> + compatible = "arm,coresight-etm3x", "arm,primecell";
>
> If I remember correctly ITM and ETMv3 are quite different - please
> remove entirely.
This was commented already. Definitely "arm,coresight-etm3x" should be
removed. arm,primecell could stay there.
Do you think that make sense to remove it completely because I expect
that connection to funnel should be aligned with others.
>
>> + reg = <0xf8805000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + out-ports {
>> + port {
>> + itm_out_port: endpoint {
>> + remote-endpoint = <&funnel0_in_port3>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + ptm at f889c000 {
>> + compatible = "arm,coresight-etm3x", "arm,primecell";
>> + reg = <0xf889c000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + cpu = <&cpu0>;
>> + out-ports {
>> + port {
>> + ptm0_out_port: endpoint {
>> + remote-endpoint = <&funnel0_in_port0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + ptm at f889d000 {
>> + compatible = "arm,coresight-etm3x", "arm,primecell";
>> + reg = <0xf889d000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + cpu = <&cpu1>;
>> + out-ports {
>> + port {
>> + ptm1_out_port: endpoint {
>> + remote-endpoint = <&funnel0_in_port1>;
>> + };
>> + };
>> + };
>> + };
>
> With the above:
>
> Reviewed-by: Mathieu Poirier <mathieu.poirier at linaro.org>
Let's discuss that ITM part first and definitely thanks for review.
Thanks,
Michal
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