[U-Boot] [PATCH v5 19/19] arm: socfpga: agilex: Enable Agilex SoC build
Ley Foon Tan
lftan.linux at gmail.com
Fri Oct 25 08:39:13 UTC 2019
On Wed, Oct 23, 2019 at 2:42 AM Simon Goldschmidt
<simon.k.r.goldschmidt at gmail.com> wrote:
>
> Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
> > Add build support for Agilex SoC.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
> > Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
>
> This does not apply any more, you'll need to rebase it (Marek has
> changed mach-socfpga/Kconfig by renaming a board).
>
Okay, noted.
Thanks.
Regards
Ley Foon
> >
> > ---
> > v5:
> > - Enable NCORE_CACHE
> >
> > v3:
> > - Disable CONFIG_USE_TINY_PRINTF
> >
> > v2:
> > - Remove IC_CLK define, use clock DM method to get i2c clock
> > - Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is enabled.
> > ---
> > arch/arm/Kconfig | 4 +-
> > arch/arm/mach-socfpga/Kconfig | 16 ++
> > arch/arm/mach-socfpga/Makefile | 9 ++
> > configs/socfpga_agilex_defconfig | 59 +++++++
> > include/configs/socfpga_agilex_socdk.h | 207 +++++++++++++++++++++++++
> > 5 files changed, 293 insertions(+), 2 deletions(-)
> > create mode 100644 configs/socfpga_agilex_defconfig
> > create mode 100644 include/configs/socfpga_agilex_socdk.h
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 3b0e315061..e6c9d19968 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -888,7 +888,7 @@ config ARCH_SOCFPGA
> > bool "Altera SOCFPGA family"
> > select ARCH_EARLY_INIT_R
> > select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
> > - select ARM64 if TARGET_SOCFPGA_STRATIX10
> > + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
> > select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
> > select DM
> > select DM_SERIAL
> > @@ -900,7 +900,7 @@ config ARCH_SOCFPGA
> > select SPL_LIBGENERIC_SUPPORT
> > select SPL_NAND_SUPPORT if SPL_NAND_DENALI
> > select SPL_OF_CONTROL
> > - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
> > + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
> > select SPL_SERIAL_SUPPORT
> > select SPL_SYSRESET
> > select SPL_WATCHDOG_SUPPORT
> > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> > index 1d914648e3..3f5c4b357f 100644
> > --- a/arch/arm/mach-socfpga/Kconfig
> > +++ b/arch/arm/mach-socfpga/Kconfig
> > @@ -26,6 +26,15 @@ config SYS_TEXT_BASE
> > default 0x01000040 if TARGET_SOCFPGA_ARRIA10
> > default 0x01000040 if TARGET_SOCFPGA_GEN5
> >
> > +config TARGET_SOCFPGA_AGILEX
> > + bool
> > + select ARMV8_MULTIENTRY
> > + select ARMV8_SET_SMPEN
> > + select ARMV8_SPIN_TABLE
> > + select CLK
> > + select NCORE_CACHE
> > + select SPL_CLK if SPL
> > +
> > config TARGET_SOCFPGA_ARRIA5
> > bool
> > select TARGET_SOCFPGA_GEN5
> > @@ -72,6 +81,10 @@ choice
> > prompt "Altera SOCFPGA board select"
> > optional
> >
> > +config TARGET_SOCFPGA_AGILEX_SOCDK
> > + bool "Intel SOCFPGA SoCDK (Agilex)"
> > + select TARGET_SOCFPGA_AGILEX
> > +
> > config TARGET_SOCFPGA_ARIES_MCVEVK
> > bool "Aries MCVEVK (Cyclone V)"
> > select TARGET_SOCFPGA_CYCLONE5
> > @@ -132,6 +145,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
> > endchoice
> >
> > config SYS_BOARD
> > + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
> > default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
> > default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
> > default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
> > @@ -148,6 +162,7 @@ config SYS_BOARD
> > default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> >
> > config SYS_VENDOR
> > + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
> > default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
> > default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
> > default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
> > @@ -165,6 +180,7 @@ config SYS_SOC
> > default "socfpga"
> >
> > config SYS_CONFIG_NAME
> > + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
> > default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
> > default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
> > default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> > index 81b6ffc675..418f543b20 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -41,6 +41,14 @@ endif
> >
> > ifdef CONFIG_TARGET_SOCFPGA_AGILEX
> > obj-y += clock_manager_agilex.o
> > +obj-y += mailbox_s10.o
> > +obj-y += misc_s10.o
> > +obj-y += mmu-arm64_s10.o
> > +obj-y += reset_manager_s10.o
> > +obj-y += system_manager_s10.o
> > +obj-y += timer_s10.o
> > +obj-y += wrap_pinmux_config_s10.o
> > +obj-y += wrap_pll_config_s10.o
> > endif
> >
> > ifdef CONFIG_SPL_BUILD
> > @@ -59,6 +67,7 @@ obj-y += firewall.o
> > obj-y += spl_s10.o
> > endif
> > ifdef CONFIG_TARGET_SOCFPGA_AGILEX
> > +obj-y += firewall.o
> > obj-y += spl_agilex.o
> > endif
> > endif
> > diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
> > new file mode 100644
> > index 0000000000..daf71ff0eb
> > --- /dev/null
> > +++ b/configs/socfpga_agilex_defconfig
> > @@ -0,0 +1,59 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_SOCFPGA=y
> > +CONFIG_SYS_TEXT_BASE=0x1000
> > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_NR_DRAM_BANKS=2
> > +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
> > +CONFIG_IDENT_STRING="socfpga_agilex"
> > +CONFIG_SPL_FS_FAT=y
> > +CONFIG_SPL_TEXT_BASE=0xFFE00000
> > +CONFIG_BOOTDELAY=5
> > +CONFIG_SPL_SPI_LOAD=y
> > +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
> > +CONFIG_HUSH_PARSER=y
> > +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
> > +CONFIG_CMD_MEMTEST=y
> > +# CONFIG_CMD_FLASH is not set
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_SF=y
> > +CONFIG_CMD_SPI=y
> > +CONFIG_CMD_USB=y
> > +CONFIG_CMD_DHCP=y
> > +CONFIG_CMD_MII=y
> > +CONFIG_CMD_PING=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_EXT4=y
> > +CONFIG_CMD_FAT=y
> > +CONFIG_CMD_FS_GENERIC=y
> > +CONFIG_OF_EMBED=y
> > +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
> > +CONFIG_ENV_IS_IN_MMC=y
> > +CONFIG_NET_RANDOM_ETHADDR=y
> > +CONFIG_SPL_DM_SEQ_ALIAS=y
> > +CONFIG_SPL_ALTERA_SDRAM=y
> > +CONFIG_DM_GPIO=y
> > +CONFIG_DWAPB_GPIO=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_DW=y
> > +CONFIG_DM_MMC=y
> > +CONFIG_MMC_DW=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SF_DEFAULT_MODE=0x2003
> > +CONFIG_SPI_FLASH_SPANSION=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_PHY_MICREL=y
> > +CONFIG_PHY_MICREL_KSZ90X1=y
> > +CONFIG_DM_ETH=y
> > +CONFIG_ETH_DESIGNWARE=y
> > +CONFIG_MII=y
> > +CONFIG_DM_RESET=y
> > +CONFIG_SPI=y
> > +CONFIG_CADENCE_QSPI=y
> > +CONFIG_DESIGNWARE_SPI=y
> > +CONFIG_USB=y
> > +CONFIG_DM_USB=y
> > +CONFIG_USB_DWC2=y
> > +CONFIG_USB_STORAGE=y
> > +# CONFIG_USE_TINY_PRINTF is not set
> > diff --git a/include/configs/socfpga_agilex_socdk.h b/include/configs/socfpga_agilex_socdk.h
> > new file mode 100644
> > index 0000000000..8ed96ed252
> > --- /dev/null
> > +++ b/include/configs/socfpga_agilex_socdk.h
> > @@ -0,0 +1,207 @@
> > +/* SPDX-License-Identifier: GPL-2.0
> > + *
> > + * Copyright (C) 2019 Intel Corporation <www.intel.com>
> > + *
> > + */
> > +
> > +#ifndef __CONFIG_SOCFGPA_AGILEX_H__
> > +#define __CONFIG_SOCFGPA_AGILEX_H__
> > +
> > +#include <asm/arch/base_addr_s10.h>
> > +#include <asm/arch/handoff_s10.h>
> > +
> > +/*
> > + * U-Boot general configurations
> > + */
> > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> > +#define CONFIG_LOADADDR 0x2000000
> > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> > +#define CONFIG_REMAKE_ELF
> > +/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
> > +#define CPU_RELEASE_ADDR 0xFFD12210
> > +#define CONFIG_SYS_CACHELINE_SIZE 64
> > +#define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */
> > +
> > +/*
> > + * U-Boot console configurations
> > + */
> > +#define CONFIG_SYS_MAXARGS 64
> > +#define CONFIG_SYS_CBSIZE 2048
> > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> > + sizeof(CONFIG_SYS_PROMPT) + 16)
> > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > +
> > +/* Extend size of kernel image for uncompression */
> > +#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
> > +
> > +/*
> > + * U-Boot run time memory configurations
> > + */
> > +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
> > +#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
> > +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
> > + + CONFIG_SYS_INIT_RAM_SIZE \
> > + - S10_HANDOFF_SIZE)
> > +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
> > +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
> > +
> > +/*
> > + * U-Boot environment configurations
> > + */
> > +#define CONFIG_ENV_SIZE 0x1000
> > +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
> > +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
> > +
> > +/*
> > + * QSPI support
> > + */
> > + #ifdef CONFIG_CADENCE_QSPI
> > +/* Enable it if you want to use dual-stacked mode */
> > +/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
> > +
> > +/* Flash device info */
> > +
> > +/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
> > +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> > +#undef CONFIG_ENV_OFFSET
> > +#undef CONFIG_ENV_SIZE
> > +#define CONFIG_ENV_OFFSET 0x710000
> > +#define CONFIG_ENV_SIZE (4 * 1024)
> > +#define CONFIG_ENV_SECT_SIZE (4 * 1024)
> > +#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */
> > +
> > +#ifndef CONFIG_SPL_BUILD
> > +#define CONFIG_MTD_DEVICE
> > +#define CONFIG_MTD_PARTITIONS
> > +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
> > +#endif /* CONFIG_SPL_BUILD */
> > +
> > +#ifndef __ASSEMBLY__
> > +unsigned int cm_get_qspi_controller_clk_hz(void);
> > +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
> > +#endif
> > +
> > +#endif /* CONFIG_CADENCE_QSPI */
> > +
> > +/*
> > + * Boot arguments passed to the boot command. The value of
> > + * CONFIG_BOOTARGS goes into the environment value "bootargs".
> > + * Do note the value will override also the chosen node in FDT blob.
> > + */
> > +#define CONFIG_BOOTARGS "earlycon"
> > +#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
> > + "run mmcboot"
> > +
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> > + "bootfile=Image\0" \
> > + "fdt_addr=8000000\0" \
> > + "fdtimage=socfpga_agilex_socdk.dtb\0" \
> > + "mmcroot=/dev/mmcblk0p2\0" \
> > + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
> > + " root=${mmcroot} rw rootwait;" \
> > + "booti ${loadaddr} - ${fdt_addr}\0" \
> > + "mmcload=mmc rescan;" \
> > + "load mmc 0:1 ${loadaddr} ${bootfile};" \
> > + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
> > + "linux_qspi_enable=if sf probe; then " \
> > + "echo Enabling QSPI at Linux DTB...;" \
> > + "fdt addr ${fdt_addr}; fdt resize;" \
> > + "fdt set /soc/spi at ff8d2000 status okay;" \
> > + "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
> > + " ${qspi_clock}; fi; \0" \
> > + "scriptaddr=0x02100000\0" \
> > + "scriptfile=u-boot.scr\0" \
> > + "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
> > + "then source ${scriptaddr}; fi\0"
> > +
> > +/*
> > + * Generic Interrupt Controller Definitions
> > + */
> > +#define CONFIG_GICV2
> > +
> > +/*
> > + * External memory configurations
> > + */
> > +#define PHYS_SDRAM_1 0x0
> > +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
> > +#define CONFIG_SYS_SDRAM_BASE 0
> > +#define CONFIG_SYS_MEMTEST_START 0
> > +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000
> > +
> > +/*
> > + * Serial / UART configurations
> > + */
> > +#define CONFIG_SYS_NS16550_CLK 100000000
> > +#define CONFIG_SYS_NS16550_MEM32
> > +
> > +/*
> > + * Timer & watchdog configurations
> > + */
> > +#define COUNTER_FREQUENCY 400000000
> > +
> > +/*
> > + * SDMMC configurations
> > + */
> > +#ifdef CONFIG_CMD_MMC
> > +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
> > +#endif
> > +/*
> > + * Flash configurations
> > + */
> > +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> > +
> > +/* Ethernet on SoC (EMAC) */
> > +#if defined(CONFIG_CMD_NET)
> > +#define CONFIG_DW_ALTDESCRIPTOR
> > +#endif /* CONFIG_CMD_NET */
> > +
> > +/*
> > + * L4 Watchdog
> > + */
> > +#ifdef CONFIG_SPL_BUILD
> > +#define CONFIG_HW_WATCHDOG
> > +#define CONFIG_DESIGNWARE_WATCHDOG
> > +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
> > +#ifndef __ASSEMBLY__
> > +#define CONFIG_DW_WDT_CLOCK_KHZ 100000
> > +#endif
> > +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000
> > +#endif
> > +
> > +/*
> > + * SPL memory layout
> > + *
> > + * On chip RAM
> > + * 0xFFE0_0000 ...... Start of OCRAM
> > + * SPL code, rwdata
> > + * empty space
> > + * 0xFFEx_xxxx ...... Top of stack (grows down)
> > + * 0xFFEy_yyyy ...... Global Data
> > + * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
> > + * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
> > + * 0xFFE3_FFFF ...... End of OCRAM
> > + *
> > + * SDRAM
> > + * 0x0000_0000 ...... Start of SDRAM_1
> > + * unused / empty space for image loading
> > + * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
> > + * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
> > + * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
> > + *
> > + */
> > +#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
> > +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
> > +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> > +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
> > +#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
> > + - CONFIG_SPL_BSS_MAX_SIZE)
> > +#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
> > +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
> > + - CONFIG_SYS_SPL_MALLOC_SIZE)
> > +
> > +/* SPL SDMMC boot support */
> > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> > +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
> > +
> > +#endif /* __CONFIG_H */
> >
>
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