[U-Boot] [PATCH 5/8] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

[Bin Meng]

Hi Rick,

On Fri, Oct 25, 2019 at 2:18 PM Andes <uboot at andestech.com> wrote:
>
> From: Rick Chen <rick at andestech.com>
>
> The mcache_ctl csr only can be manipulated in M mode.
> Add SPL_RISCV_MMODE for U-Boot SPL to control cache
> operation.
>
> Signed-off-by: Rick Chen <rick at andestech.com>
> Cc: KC Lin <kclin at andestech.com>
> Cc: Alan Kao <alankao at andestech.com>
> ---
>  arch/riscv/cpu/ax25/cache.c | 60 ++++++++++++++++++++++++++++++++++-----------
>  1 file changed, 46 insertions(+), 14 deletions(-)
>
> diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
> index 41de30c..9437e81 100644
> --- a/arch/riscv/cpu/ax25/cache.c
> +++ b/arch/riscv/cpu/ax25/cache.c
> @@ -11,18 +11,46 @@
>  #include <asm/csr.h>
>
>  #ifdef CONFIG_RISCV_NDS_CACHE
> +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)

Use CONFIG_IS_ENABLED(RISCV_MMODE)

>  /* mcctlcommand */
>  #define CCTL_REG_MCCTLCOMMAND_NUM      0x7cc
>
>  /* D-cache operation */
>  #define CCTL_L1D_WBINVAL_ALL   6
>  #endif
> +#endif
> +
> +#ifdef CONFIG_V5L2_CACHE
> +static void _cache_enable(void)
> +{
> +       struct udevice *dev = NULL;
> +
> +       uclass_find_first_device(UCLASS_CACHE, &dev);
> +
> +       if (dev)
> +               cache_enable(dev);
> +}
> +
> +static void _cache_disable(void)
> +{
> +       struct udevice *dev = NULL;
> +
> +       uclass_find_first_device(UCLASS_CACHE, &dev);
> +
> +       if (dev)
> +               cache_disable(dev);
> +}
> +#endif
>
>  void flush_dcache_all(void)
>  {
> +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
>  #ifdef CONFIG_RISCV_NDS_CACHE
> +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
>         csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
>  #endif
> +#endif
> +#endif
>  }
>
>  void flush_dcache_range(unsigned long start, unsigned long end)
> @@ -39,6 +67,7 @@ void icache_enable(void)
>  {
>  #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
>  #ifdef CONFIG_RISCV_NDS_CACHE
> +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
>         asm volatile (
>                 "csrr t1, mcache_ctl\n\t"
>                 "ori t0, t1, 0x1\n\t"
> @@ -46,12 +75,14 @@ void icache_enable(void)
>         );
>  #endif
>  #endif
> +#endif
>  }
>
>  void icache_disable(void)
>  {
>  #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
>  #ifdef CONFIG_RISCV_NDS_CACHE
> +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
>         asm volatile (
>                 "fence.i\n\t"
>                 "csrr t1, mcache_ctl\n\t"

Could you please add a patch to replace the CSR name with CSR number?
This way an upstream GCC to build this code without any issue.

> @@ -60,24 +91,23 @@ void icache_disable(void)
>         );
>  #endif
>  #endif
> +#endif
>  }
>
>  void dcache_enable(void)
>  {
>  #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
>  #ifdef CONFIG_RISCV_NDS_CACHE
> -       struct udevice *dev = NULL;
> -
> +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
>         asm volatile (
>                 "csrr t1, mcache_ctl\n\t"
>                 "ori t0, t1, 0x2\n\t"
>                 "csrw mcache_ctl, t0\n\t"
>         );
> -
> -       uclass_find_first_device(UCLASS_CACHE, &dev);
> -
> -       if (dev)
> -               cache_enable(dev);
> +#endif
> +#ifdef CONFIG_V5L2_CACHE
> +       _cache_enable();
> +#endif
>  #endif
>  #endif
>  }
> @@ -86,19 +116,17 @@ void dcache_disable(void)
>  {
>  #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
>  #ifdef CONFIG_RISCV_NDS_CACHE
> -       struct udevice *dev = NULL;
> -
> +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
>         csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
>         asm volatile (
>                 "csrr t1, mcache_ctl\n\t"
>                 "andi t0, t1, ~0x2\n\t"
>                 "csrw mcache_ctl, t0\n\t"
>         );
> -
> -       uclass_find_first_device(UCLASS_CACHE, &dev);
> -
> -       if (dev)
> -               cache_disable(dev);
> +#endif
> +#ifdef CONFIG_V5L2_CACHE
> +       _cache_disable();
> +#endif
>  #endif
>  #endif
>  }
> @@ -108,6 +136,7 @@ int icache_status(void)
>         int ret = 0;
>
>  #ifdef CONFIG_RISCV_NDS_CACHE
> +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
>         asm volatile (
>                 "csrr t1, mcache_ctl\n\t"
>                 "andi   %0, t1, 0x01\n\t"
> @@ -116,6 +145,7 @@ int icache_status(void)
>                 : "memory"
>         );
>  #endif
> +#endif
>
>         return ret;
>  }
> @@ -125,6 +155,7 @@ int dcache_status(void)
>         int ret = 0;
>
>  #ifdef CONFIG_RISCV_NDS_CACHE
> +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
>         asm volatile (
>                 "csrr t1, mcache_ctl\n\t"
>                 "andi   %0, t1, 0x02\n\t"
> @@ -133,6 +164,7 @@ int dcache_status(void)
>                 : "memory"
>         );
>  #endif
> +#endif
>
>         return ret;
>  }
> --

Regards,
Bin