[U-Boot] Pull request: u-boot-riscv/master

[uboot at andestech.com]

Hi Tom,

Please pull some riscv updates:

- Skip unavailable hart in the get_count().
- fu540 set serial env from otp.
- fu540 add mmc0 as a boot target device.
- Update fix_rela_dyn and add absolute reloc addend.
- Andestech PLIC driver will skip unavailable hart.
- Support Andestech V5L2 cache driver.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/579707002

Thanks
Rick


The following changes since commit d22c8be964a870f59d2fdab6c67cefa0c4799364:

  Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-09-01 13:33:12 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 61ce84b2cf1a6672c8e402ce8174554b25629692:

  riscv: cache: use CCTL to flush d-cache (2019-09-03 09:31:03 +0800)

----------------------------------------------------------------
Alistair Francis (1):
      sifive-fu540: config: Add mmc0 as a boot target device

Bin Meng (1):
      riscv: cpu: Skip unavailable hart in the get_count() op

Marcus Comstedt (2):
      riscv: tools: Handle addend to absolute reloc in prelink-riscv
      riscv: update fix_rela_dyn

Rick Chen (9):
      riscv: andes_plic: init plic by scanning each cpu node
      dm: cache: Add enable and disable ops for cache uclass
      dm: cache: Add enable and disable ops for sandbox and test
      dm: cache: add v5l2 cache controller driver
      riscv: ae350: use the v5l2 driver to configure the cache
      riscv: ax25: add imply v5l2 cache controller
      riscv: cache: Flush L2 cache before jump to linux
      riscv: dts: move out AE350 L2 node from cpus node
      riscv: cache: use CCTL to flush d-cache

Sagar Shrikant Kadam (1):
      riscv: sifive: fu540: set serial environment variable from otp

 arch/riscv/cpu/ax25/Kconfig             |   1 +
 arch/riscv/cpu/ax25/cache.c             |  39 +++++++++++++++++------
 arch/riscv/cpu/start.S                  |  10 +++---
 arch/riscv/dts/ae350_32.dts             |  17 ++++++----
 arch/riscv/dts/ae350_64.dts             |  17 ++++++----
 arch/riscv/lib/andes_plic.c             |  36 ++++++++++++++-------
 board/AndesTech/ax25-ae350/ax25-ae350.c |   9 ++++++
 board/sifive/fu540/fu540.c              |  18 ++++++++---
 drivers/cache/Kconfig                   |   9 ++++++
 drivers/cache/Makefile                  |   1 +
 drivers/cache/cache-uclass.c            |  20 ++++++++++++
 drivers/cache/cache-v5l2.c              | 186 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/cache/sandbox_cache.c           |  13 ++++++++
 drivers/cpu/riscv_cpu.c                 |   4 +++
 include/cache.h                         |  31 +++++++++++++++++++
 include/configs/sifive-fu540.h          |   1 +
 test/dm/cache.c                         |   2 ++
 tools/prelink-riscv.inc                 |   8 +++--
 18 files changed, 379 insertions(+), 43 deletions(-)
 create mode 100644 drivers/cache/cache-v5l2.c