[PATCH 5/7] ddr: altera: arria10: Add RAM size check

[Marek Vasut]

On 4/16/20 3:34 AM, Tan, Ley Foon wrote:
[...]
>>> +static void sdram_size_check(struct ram_info *ram) {
>>> +	phys_size_t ram_check = 0;
>>> +	phys_size_t size = ram->size;
>>> +	phys_addr_t base = ram->base;
>>> +
>>> +	debug("DDR: Running SDRAM size sanity check\n");
>>> +
>>> +	while (ram_check < size) {
>>> +		ram_check += get_ram_size((void *)(base + ram_check),
>>> +					 (phys_size_t)SZ_1G);
>>
>> Why is it running in 1 GiB steps ?
> Don't have any special reason. I'm following S10/Agilex's implementation.
> Do you prefer use smaller step size? 

Rather, why doesn't it use the entire DRAM size, without the while loop?