[PATCH 5/7] ddr: altera: arria10: Add RAM size check

[Tan, Ley Foon]

> -----Original Message-----
> From: Marek Vasut <marex at denx.de>
> Sent: Thursday, April 16, 2020 4:52 PM
> To: Tan, Ley Foon <ley.foon.tan at intel.com>; u-boot at lists.denx.de
> Cc: Ley Foon Tan <lftan.linux at gmail.com>; See, Chin Liang
> <chin.liang.see at intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>
> Subject: Re: [PATCH 5/7] ddr: altera: arria10: Add RAM size check
> 
> On 4/16/20 3:34 AM, Tan, Ley Foon wrote:
> [...]
> >>> +static void sdram_size_check(struct ram_info *ram) {
> >>> +	phys_size_t ram_check = 0;
> >>> +	phys_size_t size = ram->size;
> >>> +	phys_addr_t base = ram->base;
> >>> +
> >>> +	debug("DDR: Running SDRAM size sanity check\n");
> >>> +
> >>> +	while (ram_check < size) {
> >>> +		ram_check += get_ram_size((void *)(base + ram_check),
> >>> +					 (phys_size_t)SZ_1G);
> >>
> >> Why is it running in 1 GiB steps ?
> > Don't have any special reason. I'm following S10/Agilex's implementation.
> > Do you prefer use smaller step size?
> 
> Rather, why doesn't it use the entire DRAM size, without the while loop?
Yes, can change to entire DRAM size. Will change it.
S10/Agilex have 2 banks of memory, that's why we have the while loop for 2 banks checking.
But, A10 only have 1 bank.

Regards 
Ley Foon