[PATCH v2 14/17] x86: coral: Add I2C and TPM device-tree definitions

[Simon Glass]

Add nodes to the device tree for Cr50 and other available I2C ports. Also
enable the ACPI interrupt driver.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v2:
- Move intel-clock.h inclusion to the correct patch

 arch/x86/cpu/apollolake/Kconfig   |  1 +
 arch/x86/dts/chromebook_coral.dts | 88 +++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)

diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index ec9f993808..2ae6837f75 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -42,6 +42,7 @@ config INTEL_APOLLOLAKE
 	imply CLK
 	imply CMD_CLK
 	imply CLK_INTEL
+	imply ACPI_GPE
 
 if INTEL_APOLLOLAKE
 
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index a4a9e949e6..44a4619a66 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -20,6 +20,7 @@
 #include <asm/arch-apollolake/gpio.h>
 #include <asm/arch-apollolake/iomap.h>
 #include <asm/arch-apollolake/pm.h>
+#include <dt-bindings/clock/intel-clock.h>
 
 / {
 	model = "Google Coral";
@@ -29,6 +30,14 @@
 		cros-ec0 = &cros_ec;
 		fsp = &fsp_s;
 		spi0 = &spi;
+		i2c0 = &i2c_0;
+		i2c1 = &i2c_1;
+		i2c2 = &i2c_2;
+		i2c3 = &i2c_3;
+		i2c4 = &i2c_4;
+		i2c5 = &i2c_5;
+		i2c6 = &i2c_6;
+		i2c7 = &i2c_7;
 	};
 
 	config {
@@ -80,6 +89,13 @@
 
 	};
 
+	acpi_gpe: general-purpose-events {
+		reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
+		compatible = "intel,acpi-gpe";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	keyboard {
 		intel,duplicate-por;
 	};
@@ -248,6 +264,78 @@
 			};
 		};
 
+		i2c_0: i2c2 at 16,0 {
+			compatible = "intel,apl-i2c";
+			reg = <0x0200b010 0 0 0 0>;
+			clocks = <&clk CLK_I2C>;
+			i2c-scl-rising-time-ns = <104>;
+			i2c-scl-falling-time-ns = <52>;
+		};
+
+		i2c_1: i2c2 at 16,1 {
+			compatible = "intel,apl-i2c";
+			reg = <0x0200b110 0 0 0 0>;
+			clocks = <&clk CLK_I2C>;
+			status = "disabled";
+		};
+
+		i2c_2: i2c2 at 16,2 {
+			compatible = "intel,apl-i2c";
+			reg = <0x0200b210 0 0 0 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <400000>;
+			clocks = <&clk CLK_I2C>;
+			i2c-scl-rising-time-ns = <57>;
+			i2c-scl-falling-time-ns = <28>;
+			tpm at 50 {
+				reg = <0x50>;
+				compatible = "google,cr50";
+				u-boot,i2c-offset-len = <0>;
+				ready-gpio = <&gpio_n 28 GPIO_ACTIVE_LOW>;
+				interrupts-extended = <&acpi_gpe 0x3c 0>;
+			};
+		};
+
+		i2c_3: i2c2 at 16,3 {
+			compatible = "intel,apl-i2c";
+			reg = <0x0200b110 0 0 0 0>;
+			clocks = <&clk CLK_I2C>;
+			i2c-scl-rising-time-ns = <76>;
+			i2c-scl-falling-time-ns = <164>;
+		};
+
+		i2c_4: i2c2 at 17,0 {
+			compatible = "intel,apl-i2c";
+			reg = <0x0200b110 0 0 0 0>;
+			clocks = <&clk CLK_I2C>;
+			i2c-sda-hold-time-ns = <350>;
+			i2c-scl-rising-time-ns = <114>;
+			i2c-scl-falling-time-ns = <164>;
+		};
+
+		i2c_5: i2c2 at 17,1 {
+			compatible = "intel,apl-i2c";
+			reg = <0x0200b110 0 0 0 0>;
+			clocks = <&clk CLK_I2C>;
+			i2c-scl-rising-time-ns = <76>;
+			i2c-scl-falling-time-ns = <164>;
+		};
+
+		i2c_6: i2c2 at 17,2 {
+			compatible = "intel,apl-i2c";
+			reg = <0x0200b110 0 0 0 0>;
+			clocks = <&clk CLK_I2C>;
+			status = "disabled";
+		};
+
+		i2c_7: i2c2 at 17,3 {
+			compatible = "intel,apl-i2c";
+			reg = <0x0200b110 0 0 0 0>;
+			clocks = <&clk CLK_I2C>;
+			status = "disabled";
+		};
+
 		serial: serial at 18,2 {
 			reg = <0x0200c210 0 0 0 0>;
 			u-boot,dm-pre-reloc;
-- 
2.25.0.341.g760bfbb309-goog