[PATCH v3 11/12] riscv: Add device tree for K210
Bin Meng
bmeng.cn at gmail.com
Tue Feb 4 12:32:50 CET 2020
Hi Sean,
On Mon, Feb 3, 2020 at 4:10 AM Sean Anderson <seanga2 at gmail.com> wrote:
>
> Where possible, I have tried to find compatible drivers based on the layout of
> registers. However, I have not tested most of this functionality, and most
> devices should be considered descriptive at best. I would appreciate if anyone
> could help identify possibly compatible devices, especially for the timers
> and rtc.
>
> Should the size of a reg be the size of the documented registers, or the size
> of the address space which will be routed to that device?
Perhaps we need use the size of the address space routed to that
device, in case there is some undocumented registers we need handle.
>
> Signed-off-by: Sean Anderson <seanga2 at gmail.com>
> ---
> Changes for v3:
> - Move this patch to the end of the series
> - Add a max frequency for spi3
> - Remov unused compatible strings from spi-flash at 0
> - Add s and u to isa string
> - Fix mmu-type
> - Remove cache-line size since it is unused (in u-boot) and undocumented
> (upstream)
> - Add timer interrupts to clint0
> - Round up various registers
> - Add riscv,max-priority to plic
> - Add apb* busses, since they have clocks which need to be enabled to access
> their devices
> - Change uart compatible strings to "snps,dw-apb-uart", since that appears to
> match their registers
> - Add compatible string for wdt*
> - Add system reset device under sysctl
> - Add reset device under sysctl
> Changes for v2:
> - Model changed to "Sipeed Maix Bit" to match file name
> - Value of stdout-path fixed
> - SD card slot compatible changed to "mmc-spi-slot"
> - "jedec,spi-nor" added to spi flash compatible list
> - Aliases for spi busses added
> - timebase-frequency divided by 50 to match timer speed
> - cpu-frequency renamed to clock-frequency
> - CPUX_intc restyled to cpuX_intc
> - "kendryte,k210-soc" added to soc compatible list for future-proofing
> - PLIC handle renamed to plic0 from pic0
> - K210_RST_SOC removed from sysrst, due to not being located in the
> reset register
> - K210_RST_* numbers changed to match their bit offset within the reset
> register
> - gpio_controller restyled to gpio-controller
> - Added a second clock to the dma binding to match what the driver expects
> - Changed "snps,designware-spi" compatible string to "snps,dw-apb-ssi" to
> match the correct driver
> - Added a name to the spi clocks
> - Added reg-io-width property to spi bindings
> - Assigned a default parent to K210_CLK_SPI3
> - Removed assigned clocks for ACLK and PLLs
> - Removed u-boot,dm-pre-reloc bindings
>
> arch/riscv/dts/Makefile | 1 +
> arch/riscv/dts/k210-maix-bit.dts | 42 ++
> arch/riscv/dts/k210.dtsi | 496 ++++++++++++++++++++++++
> include/dt-bindings/reset/k210-sysctl.h | 38 ++
> 4 files changed, 577 insertions(+)
> create mode 100644 arch/riscv/dts/k210-maix-bit.dts
> create mode 100644 arch/riscv/dts/k210.dtsi
> create mode 100644 include/dt-bindings/reset/k210-sysctl.h
>
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index 4f30e6936f..3a6f96c67d 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -2,6 +2,7 @@
>
> dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> +dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
>
> targets += $(dtb-y)
>
> diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
> new file mode 100644
> index 0000000000..10f36921e0
> --- /dev/null
> +++ b/arch/riscv/dts/k210-maix-bit.dts
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Sean Anderson <seanga2 at gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "k210.dtsi"
> +
> +/ {
> + model = "Sipeed Maix Bit";
> + compatible = "sipeed,maix-bit", "kendryte,k210";
> +
> + chosen {
> + stdout-path = "serial0:115200";
> + };
> +};
> +
> +&uarths0 {
> + status = "okay";
> +};
> +
> +&spi0 {
> + status = "okay";
> + slot at 0 {
> + compatible = "mmc-spi-slot";
> + reg = <0>;
> + broken-cd;
> + disable-wp;
> + };
> +};
> +
> +&spi3 {
> + status = "okay";
> + spi-max-frequency = <120000000>;
> + spi-flash at 0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <120000000>;
> + m25p,fast-read;
> + };
> +};
> diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
> new file mode 100644
> index 0000000000..cc46b692e6
> --- /dev/null
> +++ b/arch/riscv/dts/k210.dtsi
> @@ -0,0 +1,496 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Sean Anderson <seanga2 at gmail.com>
> + */
> +
> +#include <dt-bindings/clock/k210-sysctl.h>
> +#include <dt-bindings/mfd/k210-sysctl.h>
> +#include <dt-bindings/reset/k210-sysctl.h>
> +
> +/ {
> + /*
> + * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
> + * wide, and the upper half of all addresses is ignored.
> + */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "kendryte,k210";
> +
> + aliases {
> + serial0 = &uarths0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + spi0 = &spi0;
> + spi1 = &spi1;
> + spi2 = &spi2;
> + spi3 = &spi3;
> + };
> +
> + clocks {
> + in0: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <7800000>;
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + reg = <0>;
> + compatible = "riscv";
> + riscv,isa = "rv64acdfimsu";
> + mmu-type = "sv39";
> + i-cache-size = <0x8000>;
> + d-cache-size = <0x8000>;
> + clocks = <&sysclk K210_CLK_CPU>;
> + clock-frequency = <390000000>;
I wonder there is already clocks property, why do we have another
clock-frequency property to provide duplicated information?
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "riscv,cpu-intc";
> + };
> + };
> + cpu1: cpu at 1 {
> + device_type = "cpu";
> + reg = <1>;
> + compatible = "riscv";
> + riscv,isa = "rv64acdfimsu";
> + mmu-type = "sv39";
> + i-cache-size = <0x8000>;
> + d-cache-size = <0x8000>;
> + clocks = <&sysclk K210_CLK_CPU>;
> + clock-frequency = <390000000>;
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "riscv,cpu-intc";
> + };
> + };
> + };
> +
> + sram0: memory at 80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x400000>;
> + clocks = <&sysclk K210_CLK_SRAM0>;
> + };
> +
> + sram1: memory at 80400000 {
> + device_type = "memory";
> + reg = <0x80400000 0x400000>;
> + clocks = <&sysclk K210_CLK_SRAM1>;
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + ai_reserved: ai at 80600000 {
> + reg = <0x80600000 0x200000>;
> + reusable;
> + };
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "kendryte,k210-soc", "simple-bus";
> + ranges;
> + interrupt-parent = <&plic0>;
> +
> + clint0: interrupt-controller at 2000000 {
> + compatible = "riscv,clint0";
> + reg = <0x2000000 0x1000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>;
> + clocks = <&sysclk K210_CLK_CPU>;
> + };
> +
> + plic0: interrupt-controller at c000000 {
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "kendryte,k210-plic", "riscv,plic1";
> + reg = <0xC000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>,
> + <&cpu1_intc 9>, <&cpu1_intc 11>;
> + riscv,ndev = <65>;
> + riscv,max-priority = <7>;
> + };
> +
[snip]
Regards,
Bin
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