Zybo Z7 board - fix SPL uart init bitrate

[Michal Simek]

+Luis

čt 9. 1. 2020 v 14:00 odesílatel Milan Obuch <u-boot at dino.sk> napsal:
>
> Hi,
>
> Zybo Z7 board uses 100 MHz clock for UART bitrate generator, in
> defconfig is 50 MHz listed. This error manifests itself when boot
> starts, following is seen on console:
>
> ������b
> U-Boot SPL 2019.01 (Jul 17 2019 - 21:36:54 +0200)
> mmc boot
> Trying to boot from MMC1
>
> First line is output with wrong bitrate. After changing definition to
> correct value, boot output starts correctly, now:
>
> Debug uart enabled
>
> U-Boot SPL 2019.10 (Jan 09 2020 - 08:18:37 +0100)
> mmc boot
> Trying to boot from MMC1
>
> (Please ignore version change, I just used this occasion to fix some
> other issues as well.)
>
> Patch to fix this small issue follows. As this is my first contribution
> to this project, please help me with what could be necessary to do for
> this fix to be accepted, in order to fit any custom used here...
>
> Regards,
> Milan
>
> --- configs/zynq_zybo_z7_defconfig.orig 2020-01-09 08:16:33.744969000 +0100
> +++ configs/zynq_zybo_z7_defconfig      2020-01-09 07:49:33.181891000 +0100
> @@ -5,7 +5,7 @@
>  CONFIG_SPL_STACK_R_ADDR=0x200000
>  CONFIG_SPL=y
>  CONFIG_DEBUG_UART_BASE=0xe0001000
> -CONFIG_DEBUG_UART_CLOCK=50000000
> +CONFIG_DEBUG_UART_CLOCK=100000000
>  CONFIG_DEBUG_UART=y
>  CONFIG_DISTRO_DEFAULTS=y
>  CONFIG_SYS_CUSTOM_LDSCRIPT=y

Luis: Can you please check?

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs