[PATCH 4/4] serial: serial_cortina: add UART DM driver for CAxxxx SoCs
Alex Nemirovsky
Alex.Nemirovsky at cortina-access.com
Mon Jan 20 10:53:47 CET 2020
From: Jason Li <jason.li at cortina-access.com>
Add serial UART driver support for all Cortina Access
CAxxxx family of SoCs.
Signed-off-by: Jason Li <jason.li at cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky at cortina-access.com>
---
MAINTAINERS | 4 ++
drivers/serial/Kconfig | 7 +++
drivers/serial/Makefile | 2 +-
drivers/serial/serial_cortina.c | 129 ++++++++++++++++++++++++++++++++++++++++
drivers/serial/serial_cortina.h | 83 ++++++++++++++++++++++++++
5 files changed, 224 insertions(+), 1 deletion(-)
create mode 100644 drivers/serial/serial_cortina.c
create mode 100644 drivers/serial/serial_cortina.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f9334f9..2b3282b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -181,6 +181,8 @@ F: board/cortina/common/Kconfig
F: board/cortina/common/armv8/lowlevel_init.S
F: drivers/gpio/cortina_gpio.c
F: drivers/watchdog/cortina_wdt.c
+F: drivers/serial/serial_cortina.c
+F: drivers/serial/serial_cortina.h
ARM/CZ.NIC TURRIS MOX SUPPORT
M: Marek Behun <marek.behun at nic.cz>
@@ -664,6 +666,8 @@ F: board/cortina/common/Kconfig
F: board/cortina/common/mips/*
F: drivers/gpio/cortina_gpio.c
F: drivers/watchdog/cortina_wdt.c
+F: drivers/serial/serial_cortina.c
+F: drivers/serial/serial_cortina.h
MIPS MSCC
M: Gregory CLEMENT <gregory.clement at bootlin.com>
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index ece7d87..9f76596 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -539,6 +539,13 @@ config BCM6345_SERIAL
help
Select this to enable UART on BCM6345 SoCs.
+config CORTINA_UART
+ bool "Cortina UART support"
+ depends on DM_SERIAL
+ help
+ Select this to enable UART support for Cortina-Access UART devices
+ found on CAxxxx SoCs.
+
config FSL_LINFLEXUART
bool "Freescale Linflex UART support"
depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 06ee306..c8f2db4 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -28,13 +28,13 @@ obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
endif
-
obj-$(CONFIG_ALTERA_UART) += altera_uart.o
obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
+obj-$(CONFIG_CORTINA_UART) += serial_cortina.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c
new file mode 100644
index 0000000..2b52e5d
--- /dev/null
+++ b/drivers/serial/serial_cortina.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * (C) Copyright 2020
+ * Cortina-Access Ltd.
+ * Author: Jason Li <jason.li at cortina-access.com>
+ *
+ */
+
+/* Common UART Driver for Cortina Access CAxxxx line of SoCs */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
+#include "serial_cortina.h"
+
+#define IO_WRITE(addr, val) (*(unsigned int *)(addr) = (val))
+#define IO_READ(addr) (*(unsigned int *)(addr))
+
+#ifdef CONFIG_DM_SERIAL
+
+struct ca_uart_priv {
+ void __iomem *base;
+};
+
+int ca_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct ca_uart_priv *priv = dev_get_priv(dev);
+ unsigned int uart_ctrl, baud, sample;
+
+ baud = CORTINA_UART_CLOCK / baudrate;
+
+ uart_ctrl = readl(priv->base + UCFG);
+ uart_ctrl |= (baud << 8);
+ writel(uart_ctrl, priv->base + UCFG);
+
+ sample = baud / 2;
+ sample = (sample < 7) ? 7 : sample;
+ writel(sample, priv->base + URX_SAMPLE);
+
+ return 0;
+}
+
+static int ca_serial_getc(struct udevice *dev)
+{
+ struct ca_uart_priv *priv = dev_get_priv(dev);
+ int ch;
+
+ ch = readl(priv->base + URX_DATA) & 0xFF;
+
+ return (int)ch;
+}
+
+static int ca_serial_putc(struct udevice *dev, const char ch)
+{
+ struct ca_uart_priv *priv = dev_get_priv(dev);
+ unsigned int status;
+
+ /* Retry if TX FIFO full */
+ status = readl(priv->base + UINFO);
+ while (status & UINFO_TX_FIFO_FULL)
+ status = readl(priv->base + UINFO);
+
+ writel(ch, priv->base + UTX_DATA);
+
+ return 0;
+}
+
+static int ca_serial_pending(struct udevice *dev, bool input)
+{
+ struct ca_uart_priv *priv = dev_get_priv(dev);
+ unsigned int status;
+
+ status = readl(priv->base + UINFO);
+
+ if (status & UINFO_RX_FIFO_EMPTY) /* empty */
+ return 0;
+ else /* something in RX FIFO */
+ return 1;
+}
+
+static int ca_serial_probe(struct udevice *dev)
+{
+ struct ca_uart_priv *priv = dev_get_priv(dev);
+ u32 uart_ctrl;
+
+ /* Set data, parity and stop bits */
+ uart_ctrl = UCFG_EN | UCFG_TX_EN | UCFG_RX_EN | UCFG_CHAR_8;
+ writel(uart_ctrl, priv->base + UCFG);
+
+ return 0;
+}
+
+static int ca_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ca_uart_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->base = map_physmem(addr, 0, MAP_NOCACHE);
+
+ return 0;
+}
+
+static const struct dm_serial_ops ca_serial_ops = {
+ .putc = ca_serial_putc,
+ .pending = ca_serial_pending,
+ .getc = ca_serial_getc,
+ .setbrg = ca_serial_setbrg,
+};
+
+static const struct udevice_id ca_serial_ids[] = {
+ {.compatible = "cortina,ca-uart"},
+ {}
+};
+
+U_BOOT_DRIVER(serial_cortina) = {
+.name = "serial_cortina", .id = UCLASS_SERIAL, .of_match =
+ ca_serial_ids, .ofdata_to_platdata =
+ ca_serial_ofdata_to_platdata, .priv_auto_alloc_size =
+ sizeof(struct ca_uart_priv), .probe = ca_serial_probe, .ops =
+ &ca_serial_ops,};
+#endif /* CONFIG_DM_SERIAL */
diff --git a/drivers/serial/serial_cortina.h b/drivers/serial/serial_cortina.h
new file mode 100644
index 0000000..19448f2
--- /dev/null
+++ b/drivers/serial/serial_cortina.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * u-boot/drivers/serial/serial_cortina.h
+ *
+ * Copyright (c) Cortina-Systems Limited 2020. All rights reserved.
+ * Jason Li <jason.li at cortina-systems.com>
+ *
+ */
+
+#ifndef _SERIAL_CORTINA_H_
+#define _SERIAL_CORTINA_H_
+
+/*
+ * UART Module for Cortina Access CAxxxx line of SoCs
+ */
+#define UART0_BASE_ADDR CONFIG_SYS_SERIAL0
+#define UART1_BASE_ADDR CONFIG_SYS_SERIAL1
+
+#define CONFIG_CONS_INDEX 0
+
+/* Register definitions */
+#define UCFG 0x00 /* UART config register */
+#define UFC 0x04 /* Flow Control */
+#define URX_SAMPLE 0x08 /* UART RX Sample register */
+#define URT_TUNE 0x0C /* Fine tune of UART clk */
+#define UTX_DATA 0x10 /* UART TX Character data */
+#define URX_DATA 0x14 /* UART RX Character data */
+#define UINFO 0x18 /* UART Info */
+#define UINT_EN0 0x1C /* UART Interrupt enable 0*/
+#define UINT_EN1 0x20 /* UART Interrupt enable 1*/
+#define UINT0 0x24 /* UART Interrupt 0 setting/clearing */
+#define UINT1 0x28 /* UART Interrupt 1 setting/clearing */
+#define UINT_STAT 0x2C /* UART Interrupt Status */
+
+/* UART Control Register Bit Fields */
+#define UCFG_BAUD_COUNT BIT(8)
+#define UCFG_EN BIT(7)
+#define UCFG_RX_EN BIT(6)
+#define UCFG_TX_EN BIT(5)
+#define UCFG_PARITY_EN BIT(4)
+#define UCFG_PARITY_SEL BIT(3)
+#define UCFG_2STOP_BIT BIT(2)
+#define UCFG_CNT1 BIT(1)
+#define UCFG_CNT0 BIT(0)
+#define UCFG_CHAR_5 0
+#define UCFG_CHAR_6 1
+#define UCFG_CHAR_7 2
+#define UCFG_CHAR_8 3
+
+#define UINFO_TX_FIFO_EMPTY BIT(3)
+#define UINFO_TX_FIFO_FULL BIT(2)
+#define UINFO_RX_FIFO_EMPTY BIT(1)
+#define UINFO_RX_FIFO_FULL BIT(0)
+
+#define UINT_RX_NON_EMPTY BIT(6)
+#define UINT_TX_EMPTY BIT(5)
+#define UINT_RX_UNDERRUN BIT(4)
+#define UINT_RX_OVERRUN BIT(3)
+#define UINT_RX_PARITY_ERR BIT(2)
+#define UINT_RX_STOP_ERR BIT(1)
+#define UINT_TX_OVERRUN BIT(0)
+#define UINT_MASK_ALL 0x7F
+
+/* UART CONF bits */
+#define SHF_UCONF_WL 0
+#define MSK_UCONF_WL (0x3 << SHF_UCONF_WL)
+#define VAL_UCONF_WL_5 (0x0 << SHF_UCONF_WL)
+#define VAL_UCONF_WL_6 (0x1 << SHF_UCONF_WL)
+#define VAL_UCONF_WL_7 (0x2 << SHF_UCONF_WL)
+#define VAL_UCONF_WL_8 (0x3 << SHF_UCONF_WL)
+
+#define SHF_UCONF_SB 2
+#define MSK_UCONF_SB (0x1 << SHF_UCONF_SB)
+#define VAL_UCONF_SB_1 (0x0 << SHF_UCONF_SB)
+#define VAL_UCONF_SB_2 (0x1 << SHF_UCONF_SB)
+
+#define SHF_UCONF_PM 3
+#define MSK_UCONF_PM (0x3 << SHF_UCONF_PM)
+#define VAL_UCONF_PM_N (0x0 << SHF_UCONF_PM)
+#define VAL_UCONF_PM_O (0x2 << SHF_UCONF_PM)
+#define VAL_UCONF_PM_E (0x3 << SHF_UCONF_PM)
+
+#endif /* _SERIAL_CORTINA_H_ */
--
2.7.4
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