[PATCH 1/1] arm-freescale-mx6sx: Fix imx6sx UART5 wrong iomux register configuration

[Fabio Estevam]

Hi Antonio,

Thanks for your patch.

On Sat, Jul 4, 2020 at 8:43 AM Antonio Tessarolo
<anthonytexdev at gmail.com> wrote:
>
> This patch fixes a wrong IOMUX configuration for UART5_TX of NXP’s IMX6SX
>
> ---

You missed your Signed-off-by tag.

>  arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
> b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
> index a18e08f65c..f5c8bbf0a1 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
> @@ -1615,7 +1615,7 @@ enum {
>
>   MX6_PAD_SD4_DATA5__USDHC4_DATA5                        =
> IOMUX_PAD(0x05DC, 0x0294, 0, 0x0000, 0, 0),
>   MX6_PAD_SD4_DATA5__RAWNAND_CE2_B                       =
> IOMUX_PAD(0x05DC, 0x0294, 1, 0x0000, 0, 0),
> - MX6_PAD_SD4_DATA5__UART5_TX                            =
> IOMUX_PAD(0x05DC, 0x0294, 2, 0x0850, 1, 0),
> + MX6_PAD_SD4_DATA5__UART5_TX                            =
> IOMUX_PAD(0x05DC, 0x0294, 2, 0x0000, 0, 0),

In the kernel we have:

#define MX6SX_PAD_SD4_DATA5__UART5_DCE_TX
0x0294 0x05DC 0x0000 0x2 0x0
#define MX6SX_PAD_SD4_DATA5__UART5_DTE_RX
0x0294 0x05DC 0x0850 0x2 0x1

In mx6sx_pins.h there is only the DTE definition.

I would suggest to add the DCE definition and keep the DTE one.