[PATCH] rockchip: rk3328: Add SPI support

[Kever Yang]

Hi Johannes,

The changes look good to me, but you need to split the patch into 3 patches:

- rk3328 clock driver;

- rkspi driver;

- rk3328-u-boot.dtsi

BTW: the patch no need reply-to previous mail, you can make a new thread.

Thanks,

- Kever

On 2020/7/4 上午2:08, Johannes Krottmayer wrote:
> Add U-Boot SPI support for the RK3328
>
> Signed-off-by: Johannes Krottmayer <krjdev at gmail.com>
> Cc: Kever Yang <kever.yang at rock-chips.com>
> Cc: Jagan Teki <jagan at amarulasolutions.com>
> ---
>
> It's a initial SPI support. Not sure if "rk3399_spi_params" is also
> needed. Probing of the SPI flash devices works. Tested with the
> PINE64 Rock64 board.
>
> Okay?
>
>   arch/arm/dts/rk3328-u-boot.dtsi   |  5 +++++
>   drivers/clk/rockchip/clk_rk3328.c | 31 +++++++++++++++++++++++++++++++
>   drivers/spi/rk_spi.c              |  2 ++
>   3 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
> index c69e13e11e..c980daae99 100644
> --- a/arch/arm/dts/rk3328-u-boot.dtsi
> +++ b/arch/arm/dts/rk3328-u-boot.dtsi
> @@ -7,6 +7,7 @@
>   	aliases {
>   		mmc0 = &emmc;
>   		mmc1 = &sdmmc;
> + 		spi0 = &spi0;
>   	};
>   
>   	chosen {
> @@ -66,3 +67,7 @@
>   &usb20_otg {
>   	hnp-srp-disable;
>   };
> +
> +&spi0 {
> +	u-boot,dm-pre-reloc;
> +};
> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
> index 02d3b08efa..bd95ab832b 100644
> --- a/drivers/clk/rockchip/clk_rk3328.c
> +++ b/drivers/clk/rockchip/clk_rk3328.c
> @@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
>   	return rk3328_saradc_get_clk(cru);
>   }
>   
> +static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
> +{
> +	u32 div, val;
> +
> +	val = readl(&cru->clksel_con[24]);
> +	div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
> +
> +	return DIV_TO_RATE(OSC_HZ, div);
> +}
> +
> +static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
> +{
> +	u32 src_clk_div;
> +
> +	src_clk_div = GPLL_HZ / hz;
> +	assert(src_clk_div < 128);
> +
> +	rk_clrsetreg(&cru->clksel_con[24],
> +		     CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
> +		     CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
> +		     (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
> +
> +	return rk3328_spi_get_clk(cru);
> +}
> +
>   static ulong rk3328_clk_get_rate(struct clk *clk)
>   {
>   	struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
> @@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
>   	case SCLK_SARADC:
>   		rate = rk3328_saradc_get_clk(priv->cru);
>   		break;
> +	case SCLK_SPI:
> +		rate = rk3328_spi_get_clk(priv->cru);
> +		break;
>   	default:
>   		return -ENOENT;
>   	}
> @@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
>   	case SCLK_SARADC:
>   		ret = rk3328_saradc_set_clk(priv->cru, rate);
>   		break;
> +    case SCLK_SPI:
> +		ret = rk3328_spi_set_clk(priv->cru, rate);
> +        break;
>   	case DCLK_LCDC:
>   	case SCLK_PDM:
>   	case SCLK_RTC32K:
> diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
> index 833cb04922..0495e04945 100644
> --- a/drivers/spi/rk_spi.c
> +++ b/drivers/spi/rk_spi.c
> @@ -545,7 +545,9 @@ const  struct rockchip_spi_params rk3399_spi_params = {
>   };
>   
>   static const struct udevice_id rockchip_spi_ids[] = {
> +	{ .compatible = "rockchip,rk3066-spi" },
>   	{ .compatible = "rockchip,rk3288-spi" },
> +	{ .compatible = "rockchip,rk3328-spi" },
>   	{ .compatible = "rockchip,rk3368-spi",
>   	  .data = (ulong)&rk3399_spi_params },
>   	{ .compatible = "rockchip,rk3399-spi",