[PATCHv2 06/10] pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode

[Zhiqiang Hou]

From: Xiaowei Bao <xiaowei.bao at nxp.com>

Due to the ls2085a and ls2080a use different way to set the BAR size,
so add the BAR size init code here.

Signed-off-by: Xiaowei Bao <xiaowei.bao at nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V2:
 - Rebase the patch without change intent.

 drivers/pci/pcie_layerscape_ep.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 3f22c5ef7a..20de056b8a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -173,17 +173,25 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
 			 */
 			writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
 
+			bar_base = pcie->dbi +
+				   PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
+
 			if (pcie_ep->cfg2_flag) {
-				for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+				ctrl_writel(pcie,
+					    PCIE_LCTRL0_VAL(pf, 0),
+					    PCIE_PF_VF_CTRL);
+				ls_pcie_ep_setup_bars(bar_base);
+
+				for (vf = 1; vf <= PCIE_VF_NUM; vf++) {
 					ctrl_writel(pcie,
 						    PCIE_LCTRL0_VAL(pf, vf),
 						    PCIE_PF_VF_CTRL);
+					ls_pcie_ep_setup_vf_bars(bar_base);
 				}
+			} else {
+				ls_pcie_ep_setup_bars(bar_base);
+				ls_pcie_ep_setup_vf_bars(bar_base);
 			}
-			bar_base = pcie->dbi +
-				   PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
-			ls_pcie_ep_setup_bars(bar_base);
-			ls_pcie_ep_setup_vf_bars(bar_base);
 
 			ls_pcie_ep_setup_atu(pcie_ep, pf);
 		}
-- 
2.17.1