[PATCH v3 4/4] x86: fsp: Support a warning message when DRAM init is slow

[Bin Meng]

On Fri, Jul 10, 2020 at 8:43 AM Simon Glass <sjg at chromium.org> wrote:
>
> With DDR4, Intel SOCs take quite a long time to init their memory. During
> this time, if the user is watching, it looks like SPL has hung. Add a
> message in this case.
>
> This works by adding a return code to fspm_update_config() that indicates
> whether MRC data was found and a new property to the device tree.
>
> Also add one more debug message while starting.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> Reviewed-by: Wolfgang Wallner <wolfgang.wallner at br-automation.com>
> Tested-by: Wolfgang Wallner <wolfgang.wallner at br-automation.com>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Use the three-argument CONFIG_IS_ENABLED() instead of IF_ENABLED_INT()
> - Update binding to mention timing for coral and a 1GB APL board
> - Drop patch 'kconfig: Add support for conditional values'
>
>  arch/x86/cpu/apollolake/fsp_m.c               | 12 ++++++++--
>  arch/x86/dts/chromebook_coral.dts             |  1 +
>  arch/x86/include/asm/fsp2/fsp_internal.h      |  3 ++-
>  arch/x86/lib/fsp2/fsp_meminit.c               | 24 +++++++++++++++----
>  .../fsp/fsp2/apollolake/fsp-m.txt             |  4 ++++
>  5 files changed, 36 insertions(+), 8 deletions(-)
>

applied to u-boot-x86, thanks!