[PATCH] arm: mach-k3: Clean non-coherent lines out of L3 cache

Andrew F. Davis afd at ti.com
Wed Jul 15 23:02:36 CEST 2020

When switching on or off the ARM caches some care must be taken to ensure
existing cache line allocations are not left in an inconsistent state.
An example of this is when cache lines are considered non-shared by
and L3 controller even though the lines are shared. To prevent these
and other issues all cache lines should be cleared before enabling
or disabling a coherent master's cache. ARM cores and many L3 controllers
provide a way to efficiently clean out all cache lines to allow for
this, unfortunately there is no such easy way to do this on current K3
MSMC based systems.

We could explicitly clean out every valid external address tracked by
MSMC (all of DRAM), or we could attempt to identify only the set of
addresses accessed by a given boot stage and flush only those
specifically. This patch attempts the latter. We start with cleaning the
SPL load address. More addresses can be added here later as they are

Note that we perform a flush operation for both the flush and invalidate
operations, this is not a typo. We do this to avoid the situation that
some ARM cores will promote an invalidate to a clean+invalidate, but only
emit the invalidation operation externally, leading to a loss of data.

Signed-off-by: Andrew F. Davis <afd at ti.com>
Tested-by: Faiz Abbas <faiz_abbas at ti.com>
 arch/arm/mach-k3/Makefile |  1 +
 arch/arm/mach-k3/cache.S  | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+)
 create mode 100644 arch/arm/mach-k3/cache.S

diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 028015ed66..7572f56925 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
 obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
+obj-$(CONFIG_ARM64) += cache.o
 ifeq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
diff --git a/arch/arm/mach-k3/cache.S b/arch/arm/mach-k3/cache.S
new file mode 100644
index 0000000000..a5717ea203
--- /dev/null
+++ b/arch/arm/mach-k3/cache.S
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andrew F. Davis <afd at ti.com>
+ */
+#include <config.h>
+#include <linux/linkage.h>
+#if defined(CONFIG_SPL_BUILD)
+	/* Invalidate SPL address range */
+	add x1, x0, #CONFIG_SPL_MAX_SIZE
+	b __asm_flush_dcache_range
+	/* Flush SPL address range */
+	add x1, x0, #CONFIG_SPL_MAX_SIZE
+	b __asm_flush_dcache_range

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