[PATCH v1 2/4] usb: xhci: xhci_mem_init: Use cpu_to_le64() and not xhci_writeq()
Stefan Roese
sr at denx.de
Fri Jul 17 12:04:17 CEST 2020
On 17.07.20 07:24, Bin Meng wrote:
> Hi Stefan,
>
> On Thu, Jul 2, 2020 at 4:47 PM Stefan Roese <sr at denx.de> wrote:
>>
>> xhci_writeq() makes the CPU->LE swapping only when addressing registers
>> in the xHCI controller address range and not in the local memory (RAM).
>
> Is the above behavior exposed by the MIPS platform's writel()?
Not sure what you mean with this. Without this patch, xhci_writeq()
will not swap on Octeon MIPS, as the destination address is located
in local memory (DDR). Using the xhci_read/write accessor functions
should be restricted to accessing the controller registers.
BTW: The Octeon MIPS writel will swap to little-endian, when the
location is in the xHCI controller address space (and PCI etc). This
support for selective swapping is not pushed into mainline yet. I
will send it in some follow up patches.
Thanks,
Stefan
>> We need to use cpu_to_le64() here to ensure that the conversion is done
>> correctly.
>>
>> Signed-off-by: Stefan Roese <sr at denx.de>
>> Cc: Bin Meng <bmeng.cn at gmail.com>
>> Cc: Marek Vasut <marex at denx.de>
>> ---
>>
>> drivers/usb/host/xhci-mem.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
>> index bd959b4093..3b805ecb9e 100644
>> --- a/drivers/usb/host/xhci-mem.c
>> +++ b/drivers/usb/host/xhci-mem.c
>> @@ -562,7 +562,7 @@ int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
>> trb_64 = 0;
>> trb_64 = (uintptr_t)seg->trbs;
>> struct xhci_erst_entry *entry = &ctrl->erst.entries[val];
>> - xhci_writeq(&entry->seg_addr, trb_64);
>> + entry->seg_addr = cpu_to_le64(trb_64);
>> entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
>> entry->rsvd = 0;
>> seg = seg->next;
>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
>
> Regards,
> Bin
>
Thanks,
Stefan
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