[v3, 09/11] mmc: fsl_esdhc: fix eMMC HS400 stability issue

Yangbo Lu yangbo.lu at nxp.com
Thu Jul 23 06:30:14 CEST 2020

There was a fix-up for eMMC HS400 stability issue in Linux.

Patch link:

Currently only LX2160A eSDHC supports eMMC HS400. According to
a large number of tests, eMMC HS400 failed to work at 150MHz,
and for a few boards failed to work at 175MHz. But eMMC HS400
worked fine on 200MHz. We hadn't found the root cause but
setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain
seemed to resovle this issue. Let's use this as fixup for now.

Introduce the fix-up in u-boot since the issue could be reproduced
in u-boot too.

Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
Changes for v2:
	- Added this patch.
Changes for v3:
	- None.
 drivers/mmc/fsl_esdhc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 716f53e..20e3ff9 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -644,7 +644,10 @@ static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
 		esdhc_setbits32(&regs->sdclkctl, CMD_CLK_CTL);
 		esdhc_clock_control(priv, true);
-		esdhc_setbits32(&regs->dllcfg0, DLL_ENABLE | DLL_FREQ_SEL);
+		if (priv->clock == 200000000)
+			esdhc_setbits32(&regs->dllcfg0, DLL_FREQ_SEL);
+		esdhc_setbits32(&regs->dllcfg0, DLL_ENABLE);
 		esdhc_setbits32(&regs->tbctl, HS400_WNDW_ADJUST);
 		esdhc_clock_control(priv, false);

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