[PATCH 1/3] arm: socfpga: arria10: Add qts-filter for Arria10 socfpga
Ley Foon Tan
ley.foon.tan at intel.com
Thu Jul 23 09:55:41 CEST 2020
From: Dalon Westergreen <dalon.westergreen at intel.com>
Add a script to process HPS handoff data and generate a header
for inclusion in u-boot specific devicetree addons. The header
should be included in the top level of u-boot.dtsi.
Signed-off-by: Dalon Westergreen <dalon.westergreen at intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
---
arch/arm/mach-socfpga/qts-filter-a10.sh | 141 ++++++++++++++++++++++++
doc/README.socfpga | 37 ++++++-
2 files changed, 174 insertions(+), 4 deletions(-)
create mode 100755 arch/arm/mach-socfpga/qts-filter-a10.sh
diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh b/arch/arm/mach-socfpga/qts-filter-a10.sh
new file mode 100755
index 000000000000..57d77e8e12c6
--- /dev/null
+++ b/arch/arm/mach-socfpga/qts-filter-a10.sh
@@ -0,0 +1,141 @@
+#!/bin/bash
+
+#
+# helper function to convert from DOS to Unix, if necessary, and handle
+# lines ending in '\'.
+#
+fix_newlines_in_macros() {
+ sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
+}
+
+#filter out only what we need from a10 hps.xml
+grep_a10_hps_config() {
+ egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER"
+}
+
+#
+# Process hps.xml
+# $1: hps.xml
+# $2: Output File
+#
+process_a10_hps_config() {
+ hps_xml="$1"
+ outfile="$2"
+
+ (cat << EOF
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Intel Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+EOF
+
+ echo "/* Clocks */"
+ fix_newlines_in_macros \
+ ${hps_xml} | egrep "clk_hz" |
+ awk -F"'" '{ gsub("\\.","_",$2) ; \
+ print "#define" " " toupper($2) " " $4}' |
+ sed 's/\.[0-9]//' |
+ sed 's/I_CLK_MGR_//' |
+ sort
+ fix_newlines_in_macros \
+ ${hps_xml} | egrep "i_clk_mgr_mainpll" |
+ awk -F"'" '{ gsub("\\.","_",$2) ; \
+ print "#define" " " toupper($2) " " $4}' |
+ sed 's/\.[0-9]//' |
+ sed 's/I_CLK_MGR_//' |
+ sort
+ fix_newlines_in_macros \
+ ${hps_xml} | egrep "i_clk_mgr_perpll" |
+ awk -F"'" '{ gsub("\\.","_",$2) ; \
+ print "#define" " " toupper($2) " " $4}' |
+ sed 's/\.[0-9]//' |
+ sed 's/I_CLK_MGR_//' |
+ sort
+ fix_newlines_in_macros \
+ ${hps_xml} | egrep "i_clk_mgr_clkmgr" |
+ awk -F"'" '{ gsub("\\.","_",$2) ; \
+ print "#define" " " toupper($2) " " $4}' |
+ sed 's/\.[0-9]//' |
+ sed 's/I_CLK_MGR_//' |
+ sort
+ fix_newlines_in_macros \
+ ${hps_xml} | egrep "i_clk_mgr_alteragrp" |
+ awk -F"'" '{ gsub("\\.","_",$2) ; \
+ print "#define" " " toupper($2) " " $4}' |
+ sed 's/\.[0-9]//' |
+ sed 's/I_CLK_MGR_//' |
+ sort
+ echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\"
+ echo " (ALTERAGRP_MPUCLK_MAINCNT))"
+ echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\"
+ echo " (ALTERAGRP_NOCCLK_MAINCNT))"
+
+ echo
+ echo "/* Pin Mux Configuration */"
+ fix_newlines_in_macros \
+ ${hps_xml} | egrep "i_io48_pin_mux" |
+ awk -F"'" '{ gsub("\\.","_",$2) ; \
+ print "#define" " " toupper($2) " " $4}' |
+ sed 's/I_IO48_PIN_MUX_//' |
+ sed 's/SHARED_3V_IO_GRP_//' |
+ sed 's/FPGA_INTERFACE_GRP_//' |
+ sed 's/DEDICATED_IO_GRP_//' |
+ sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
+ sort
+
+ echo
+ echo "/* Bridge Configuration */"
+ fix_newlines_in_macros \
+ ${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" |
+ awk -F"'" '{ gsub("\\.","_",$2) ; \
+ print "#define" " " toupper($2) " " $4}' |
+ sed 's/true/1/' |
+ sed 's/false/0/' |
+ sort
+
+ echo
+ echo "/* Voltage Select for Config IO */"
+ echo "#define CONFIG_IO_BANK_VSEL \\"
+ echo " (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\"
+ echo " (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
+
+ echo
+ echo "/* Macro for Config IO bit mapping */"
+ echo -n "#define CONFIG_IO_MACRO(NAME) "
+ echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
+ echo " ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\"
+ echo " ((NAME ## _WK_PU_EN & 0x1) << 16) | \\"
+ echo " ((NAME ## _PU_SLW_RT & 0x1) << 13) | \\"
+ echo " ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\"
+ echo " ((NAME ## _PD_SLW_RT & 0x1) << 5) | \\"
+ echo " (NAME ## _PD_DRV_STRG & 0x1f))"
+
+ cat << EOF
+
+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
+EOF
+ ) > "${outfile}"
+}
+
+usage() {
+ echo "$0 [hps_xml] [output_file]"
+ echo "Process QTS-generated hps.xml into devicetree header."
+ echo ""
+ echo " hps_xml - hps.xml file from hps_isw_handoff"
+ echo " output_file - Output header file for dtsi include"
+ echo ""
+}
+
+hps_xml="$1"
+outfile="$2"
+
+if [ "$#" -ne 2 ] ; then
+ usage
+ exit 1
+fi
+
+process_a10_hps_config "${hps_xml}" "${outfile}"
diff --git a/doc/README.socfpga b/doc/README.socfpga
index cae0ef1a2146..4d73398eb97f 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -16,9 +16,9 @@ controller support within SOCFPGA
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
---------------------------------------------------
-Generating the handoff header files for U-Boot SPL
---------------------------------------------------
+---------------------------------------------------------------------
+Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL
+---------------------------------------------------------------------
This text is assuming quartus 16.1, but newer versions will probably work just fine too;
verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB).
@@ -32,7 +32,7 @@ Rebuilding your Quartus project
Choose one of the follwing methods, either command line or GUI.
-Using the comaand line
+Using the command line
~~~~~~~~~~~~~~~~~~~~~~
First run the embedded command shell, using your path to the Quartus install:
@@ -147,3 +147,32 @@ Note: file sizes will differ slightly depending on the selected board.
Now your board is ready for full mainline support including U-Boot SPL.
The Preloader will not be needed any more.
+
+----------------------------------------------------------
+Arria 10 generating the handoff header files for U-Boot SPL
+----------------------------------------------------------
+
+A header file for inclusion in a devicetree for Arria10 can be generated
+by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml
+file generated during the FPGA project compilation. The header contains
+all PLL, clock, pinmux, and bridge configurations required.
+
+Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example
+that includes use of the generated handoff header.
+
+Devicetree header generation
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The qts-filter-a10.sh script can process the compile time genetated hps.xml
+to create the appropriate devicetree header.
+
+
+ $ ./arch/arm/mach-socfpga/qts-filter-a10.sh \
+ <hps_xml> \
+ <output_file>
+
+ hps_xml - hps_isw_handoff/hps.xml from Quartus project
+ output_file - Output filename and location for header file
+
+The script generates a single header file names <output_file> that should
+be placed in arch/arm/dts.
--
2.19.0
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