[PATCH 6/6] riscv: Update SiFive device tree for new CLINT driver

[Bin Meng]

Hi Sean,

On Wed, Jul 22, 2020 at 11:51 PM Sean Anderson <seanga2 at gmail.com> wrote:
>
> We may need to add a clock-frequency binding like for the K210.
>
> Signed-off-by: Sean Anderson <seanga2 at gmail.com>
> ---
> This patch builds but has NOT been tested.
>
>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> index afdb4f4402..e56bfc7595 100644
> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> @@ -55,8 +55,13 @@
>                 };
>                 clint at 2000000 {
>                         compatible = "riscv,clint0";
> -                       interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
> +                       interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> +                                              &cpu1_intc 3 &cpu1_intc 7
> +                                              &cpu2_intc 3 &cpu2_intc 7
> +                                              &cpu3_intc 3 &cpu3_intc 7
> +                                              &cpu4_intc 3 &cpu4_intc 7>;
>                         reg = <0x0 0x2000000 0x0 0xc0000>;
> +                       clocks = <&prci PRCI_CLK_COREPLL>;

This looks wrong to me. The CLINT timer frequency should come from the RTC node.

+Pragnesh Patel

+Sagar Kadam

>                         u-boot,dm-spl;
>                 };
>                 dmc: dmc at 100b0000 {

Regards,
Bin