[RESEND, V2, 1/2] eth: mtk-eth: enable mt7629 sgmii mode support in mediatek eth driver

[MarkLee]

The sgmii mode init flow is almost the same for all mediatek SoC, the
only difference is the register offset(SGMSYS_GEN2_SPEED) is 0x2028
in the old chip(mt7622) but changed to 0x128 for the newer chip(mt7629 
and the following chips).

Signed-off-by: MarkLee <Mark-MC.Lee at mediatek.com>
---
V2: use driver private data from dts to decide the register offset
  (SGMSYS_GEN2_SPEED) instead of check #ifdefs in drivers.
---
 drivers/net/mtk_eth.c | 3 ++-
 drivers/net/mtk_eth.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index 5ffcc5313d..f73db4ff12 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1090,7 +1090,8 @@ static int mtk_phy_probe(struct udevice *dev)
 static void mtk_sgmii_init(struct mtk_eth_priv *priv)
 {
 	/* Set SGMII GEN2 speed(2.5G) */
-	clrsetbits_le32(priv->sgmii_base + SGMSYS_GEN2_SPEED,
+	clrsetbits_le32(priv->sgmii_base + ((priv->soc == SOC_MT7622) ?
+			SGMSYS_GEN2_SPEED : SGMSYS_GEN2_SPEED_V2),
 			SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
 
 	/* Disable SGMII AN */
diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
index f2940c9996..6149fec07e 100644
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -45,6 +45,7 @@
 #define SGMII_PHYA_PWD			BIT(4)
 
 #define SGMSYS_GEN2_SPEED		0x2028
+#define SGMSYS_GEN2_SPEED_V2		0x128
 #define SGMSYS_SPEED_2500		BIT(2)
 
 /* Frame Engine Registers */
-- 
2.17.1