[U-Boot] [PATCH V3 15/27] imx8m: Fix MMU table issue for OPTEE memory
Igor Opaniuk
igor.opaniuk at gmail.com
Thu Mar 5 11:36:05 CET 2020
Hi Peng,
On Thu, Mar 5, 2020 at 2:50 AM Peng Fan <peng.fan at nxp.com> wrote:
>
> > Subject: Re: [U-Boot] [PATCH V3 15/27] imx8m: Fix MMU table issue for
> > OPTEE memory
> >
> > Hi Peng,
> >
> > On Tue, Aug 27, 2019 at 9:38 AM Peng Fan <peng.fan at nxp.com> wrote:
> > >
> > > When running with OPTEE, the MMU table in u-boot does not remove the
> > > OPTEE memory from its settings. So ARM speculative prefetch in u-boot
> > > may access that OPTEE memory. Due to trust zone is enabled by OPTEE
> > > and that memory is set to secure access, then the speculative prefetch
> > > will fail and cause various memory issue in u-boot.
> > > The fail address register and int_status register in trustzone has
> > > logged that speculative access from u-boot.
> > >
> > > Signed-off-by: Peng Fan <peng.fan at nxp.com>
> > > ---
> > > arch/arm/mach-imx/imx8m/soc.c | 20 ++++++++++++++++++--
> > > 1 file changed, 18 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-imx/imx8m/soc.c
> > > b/arch/arm/mach-imx/imx8m/soc.c index 5115471eff..dd393b581b
> > 100644
> > > --- a/arch/arm/mach-imx/imx8m/soc.c
> > > +++ b/arch/arm/mach-imx/imx8m/soc.c
> > > @@ -112,16 +112,18 @@ static struct mm_region imx8m_mem_map[] = {
> > > /* DRAM1 */
> > > .virt = 0x40000000UL,
> > > .phys = 0x40000000UL,
> > > - .size = 0xC0000000UL,
> > > + .size = PHYS_SDRAM_SIZE,
> > > .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> > > PTE_BLOCK_OUTER_SHARE
> > > +#ifdef PHYS_SDRAM_2_SIZE
> > > }, {
> > > /* DRAM2 */
> > > .virt = 0x100000000UL,
> > > .phys = 0x100000000UL,
> > > - .size = 0x040000000UL,
> > > + .size = PHYS_SDRAM_2_SIZE,
> > > .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> > > PTE_BLOCK_OUTER_SHARE
> > > +#endif
> > > }, {
> > > /* List terminator */
> > > 0,
> > > @@ -130,6 +132,20 @@ static struct mm_region imx8m_mem_map[] = {
> > >
> > > struct mm_region *mem_map = imx8m_mem_map;
> > >
> > > +void enable_caches(void)
> > > +{
> > > + /*
> > > + * If OPTEE runs, remove OPTEE memory from MMU table to
> > > + * avoid speculative prefetch. OPTEE runs at the top of
> > > + * the first memory bank
> > > + */
> > > + if (rom_pointer[1])
> > > + imx8m_mem_map[5].size -= rom_pointer[1];
> > > +
> > > + icache_enable();
> > > + dcache_enable();
> > > +}
> > > +
> > > static u32 get_cpu_variant_type(u32 type) {
> > > struct ocotp_regs *ocotp = (struct ocotp_regs
> > > *)OCOTP_BASE_ADDR;
> > > --
> > > 2.16.4
> > >
> > > _______________________________________________
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> > > U-Boot at lists.denx.de
> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > >
> > s.denx.de%2Flistinfo%2Fu-boot&data=02%7C01%7Cpeng.fan%40nxp.co
> > m%7C
> > >
> > abfc9387a622474e599508d7c049395c%7C686ea1d3bc2b4c6fa92cd99c5c30
> > 1635%7C
> > >
> > 0%7C0%7C637189293044493841&sdata=fMrSP%2BMAzI20VMGhXm0U
> > 6kejjaClNOo
> > > bFjB4HVkTt%2Fs%3D&reserved=0
> >
> > Unfortunately, I'm still facing a similar issue when OP-TEE is loaded on
> > iMX8MM-based module, despite BL32_BASE(0xbe000000) +
> > BL32_SIZE(0x2000000) region is excluded.
> > Based on debug ouput the latest one is:
> > ....
> > idx=2 PTE 00000000bfff7010 at level 1: bfffd003 Checking if pte fits for
> > virt=bde00000 size=200000 blocksize=40000000
> > addr=bde00000 level=2
> > idx=2 PTE 00000000bfff7010 at level 1: bfffd003 idx=1ef PTE
> > 00000000bfffdf78 at level 2: 0 Checking if pte fits for virt=bde00000
> > size=200000 blocksize=200000 Setting PTE 00000000bfffdf78 to block
> > virt=bde00000
>
> Wired. If this is true, this is bug in u-boot MMU part.
Sorry fot the noise, that was wrong dram initiailization (I've forgot
to take into account rom_pointer[1] value)
The fix for my board is:
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 16b9fa1ec1..024c0bd183 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
@@ -13,7 +14,12 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ /* rom_pointer[1] contains the size of TEE occupies */
+ if (rom_pointer[1])
+ gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+ else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
return 0;
}
This bug is actual for imx8mm_evk also.
>
> Regards,
> Peng.
>
> >
> >
> > U-Boot hangs just after writing to System Control Register in
> > arch/arm/cpu/armv8/cache_v8.c:419:
> >
> > /* enable the mmu */
> > set_sctlr(get_sctlr() | CR_M);
> >
> > In my setup mainline U-Boot/TF-A/OP-TEE are used:
> > u-boot: 133276f14a ("Merge branch '2020-02-25-master-imports'")
> > tf-a: 6e46981f84 ("Merge "Update pathnames in maintainers.rst file"
> > into integration")
> > op-tee: a67dc424ff ("ta: pkcs11: API for slot/token information")
> >
> > OP-TEE is compiled with these flags:
> > CFG_ARM64_core=y
> > CFG_NXP_CAAM=n
> > CFG_NXPCRYPT=n
> > PLATFORM=imx-mx8mmevk
> > CFG_TEE_CORE_LOG_LEVEL=4
> > DEBUG=y
> > CFG_TEE_CORE_DEBUG=y
> >
> > With DCACHE disabled obviously everything works. Also I don't face any
> > issues if TF-A is compiled without SPD=opteed.
> >
> > Maybe it rings the bell and you already saw similar issues before?
> >
> > Thanks
> >
> > --
> > Best regards - Freundliche Grüsse - Meilleures salutations
> >
> > Igor Opaniuk
> >
> > mailto: igor.opaniuk at gmail.com
> > skype: igor.opanyuk
> > +380 (93) 836 40 67
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fua.linke
> > din.com%2Fin%2Fiopaniuk&data=02%7C01%7Cpeng.fan%40nxp.com%7
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> > fbL%2FGn2H%2FBilRgKeQe5CHaUt0BjKP4%3D&reserved=0
--
Best regards - Freundliche Grüsse - Meilleures salutations
Igor Opaniuk
mailto: igor.opaniuk at gmail.com
skype: igor.opanyuk
+380 (93) 836 40 67
http://ua.linkedin.com/in/iopaniuk
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