[PATCH v2 10/12] phy: atheros: add device tree bindings and config
joe.hershberger at ni.com
Fri Mar 6 00:09:29 CET 2020
On Thu, Dec 5, 2019 at 5:04 PM Michael Walle <michael at walle.cc> wrote:
> Add support for configuring the CLK_25M pin as well as the RGMII I/O
> voltage by the device tree.
> By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
> But this output can also be changed by software to other frequencies.
> This commit introduces a generic way to configure this output.
> Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
> An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
> option needs an external supply voltage. This commit adds support to
> switch the internal LDO to 1.8V.
> Signed-off-by: Michael Walle <michael at walle.cc>
Acked-by: Joe Hershberger <joe.hershberger at ni.com>
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