[PATCH v2 1/3] arm: socfpga: Add onchip RAM size macro

[Ley Foon Tan]

Add OCRAM size macro for Gen5 and Arria 10.

Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 ++
 arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 929c413e0392..b947cc07291c 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -47,4 +47,6 @@
 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS		0xffd13400
 #define SOCFPGA_NOC_FW_H2F_SCR_OFST		0xffd13500
 
+#define SOCFPGA_PHYS_OCRAM_SIZE			0x40000
+
 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
index 2725e9fcc345..da966fb45836 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
@@ -59,4 +59,6 @@
 #define SOCFPGA_DMANONSECURE_ADDRESS	0xffe00000
 #define SOCFPGA_DMASECURE_ADDRESS	0xffe01000
 
+#define SOCFPGA_PHYS_OCRAM_SIZE		0x10000
+
 #endif /* _SOCFPGA_BASE_ADDRS_H_ */
-- 
2.19.0