[PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager driver
Ang, Chee Hong
chee.hong.ang at intel.com
Wed Mar 11 08:03:14 CET 2020
> On 3/11/20 7:35 AM, Ang, Chee Hong wrote:
> >>>> Hmm, so you're just using misc_ops to still issue generic writes.
> >>>> From the discussion with Marek in the last version, I would have
> >>>> thought you wanted to create a higher level API instead of still
> >>>> tunnelling
> >> reads and writes?
> >> Any response to this?
> > Sorry, I missed this one
> > Actually I have created higher level API in ATF but I switch back to
> > generic writes because the higher level API in ATF doesn't apply to Gen5/A10
> ATF doesn't apply to Gen5/A10 either though ?
> > Here is what I will do in my revision in system manager driver:
> > 1) drop misc_read/misc_write and use misc_ioctl instead in system
> > manager
> > 2) misc_ioctl() will support configuring EMAC/SDMMC
> > 3) For SoC64 running at EL2 (non-secure), misc_iotctl() will invoke
> > the ATF's 'high level' API
> > 4) For Gen/A10 and SoC64 running at EL3 (secure), the driver just
> > configure the EMAC/SDMMC registers in misc_iotcl() Is this better ?
> Can't you configure everything in secure-mode and just not configure anything
> anymore in non-secure mode ?
Yes. I can move all these configurations to SPL(secure mode) and remove them from EMAC/SDMMC drivers.
This will affect all platforms even Gen5/A10 even they don’t have the secure access problems.
All Gen5/A10/S10/Agilex share the same EMAC/SDMMC drivers.
For EMAC driver such as 'drivers/net/dwmac_socfpga.c', moving the PHY settings into SPL
will leave this EMAC driver just asserting reset to EMAC controller and nothing else.
EMAC node has to be enabled for SPL device tree as well for MAC PHY configuration.
If you think it is OK to split the SDMMC clock and EMAC PHY configuration from SDMMC and EMAC drivers
and put them in SPL, we can go this way.
I can just drop the 'system manager' driver and all those high level APIs in ATF.
> Best regards,
> Marek Vasut
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