[PATCH v5 05/14] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files

[Bin Meng]

On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
<pragnesh.patel at sifive.com> wrote:
>
> Devicetree files in FU540 platform is synced from Linux, like other
> platforms does. Apart from these u-boot in FU540 would also require

nits: U-Boot

> some u-boot specific node like clint.

ditto

>
> So, create board specific -u-boot.dtsi files. This would help of
> maintain u-boot specific changes separately without touching Linux

ditto

> dts(i) files which indeed easy for syncing from Linux between
> releases.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
> Reviewed-by: Anup Patel <anup.patel at wdc.com>
> ---
>  arch/riscv/dts/fu540-c000-u-boot.dtsi         | 42 +++++++++++++++++++
>  .../dts/hifive-unleashed-a00-u-boot.dtsi      | 16 +++++++
>  2 files changed, 58 insertions(+)
>
> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> index 31fd113c7d..2d3d62801f 100644
> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> @@ -4,11 +4,53 @@
>   */
>
>  / {
> +       cpus {
> +               u-boot,dm-spl;
> +               cpu0: cpu at 0 {
> +                       u-boot,dm-spl;
> +                       status = "okay";
> +                       cpu0_intc: interrupt-controller {
> +                               u-boot,dm-spl;
> +                       };
> +               };
> +               cpu1: cpu at 1 {
> +                       u-boot,dm-spl;
> +               };
> +               cpu2: cpu at 2 {
> +                       u-boot,dm-spl;
> +               };
> +               cpu3: cpu at 3 {
> +                       u-boot,dm-spl;
> +               };
> +               cpu4: cpu at 4 {
> +                       u-boot,dm-spl;
> +               };
> +       };
> +
>         soc {
> +               u-boot,dm-spl;
>                 otp: otp at 10070000 {
>                         compatible = "sifive,fu540-otp";
>                         reg = <0x0 0x10070000 0x0 0x0FFF>;
>                         fuse-count = <0x1000>;
>                 };
> +               clint at 2000000 {
> +                       compatible = "riscv,clint0";
> +                       interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 >;

Looks this property value is incomplete: missing cpu1/2/3/4_intc ?

> +                       reg = <0x0 0x2000000 0x0 0xc0000>;
> +                       u-boot,dm-spl;
> +               };
>         };
>  };
> +
> +&prci {
> +       u-boot,dm-spl;
> +};
> +
> +&uart0 {
> +       u-boot,dm-spl;
> +};
> +
> +&qspi2 {
> +       u-boot,dm-spl;
> +};
> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> index bec0d19134..cce1bd943e 100644
> --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> @@ -4,3 +4,19 @@
>   */
>
>  #include "fu540-c000-u-boot.dtsi"
> +
> +/ {
> +       hfclk {
> +               u-boot,dm-spl;
> +       };
> +
> +       rtcclk {
> +               u-boot,dm-spl;
> +       };
> +};
> +
> +&qspi2 {
> +       mmc at 0 {
> +               u-boot,dm-spl;
> +       };
> +};
> --

Looks good otherwise

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>