[PATCH] riscv: ax25: cache: Remove SPL_RISCV_MMODE config check

Pragnesh Patel pragnesh.patel at sifive.com
Sat Mar 14 11:47:06 CET 2020


>-----Original Message-----
>From: Bin Meng <bmeng.cn at gmail.com>
>Sent: 14 March 2020 14:41
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Atish Patra
><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Paul
>Walmsley <paul.walmsley at sifive.com>; Rick Chen <rick at andestech.com>;
>Simon Glass <sjg at chromium.org>; Alexey Brodkin
><abrodkin at synopsys.com>; Trevor Woerner <trevor at toganlabs.com>
>Subject: Re: [PATCH] riscv: ax25: cache: Remove SPL_RISCV_MMODE config
>On Sat, Mar 14, 2020 at 4:48 PM Pragnesh Patel <pragnesh.patel at sifive.com>
>> CONFIG_IS_ENABLED(FOO) will check FOO config option for U-boot proper,
>nits: U-Boot

Will update in v2.

>> SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()
>> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
>> ---
>>  arch/riscv/cpu/ax25/cache.c | 16 ++++++++--------
>>  1 file changed, 8 insertions(+), 8 deletions(-)
>Reviewed-by: Bin Meng <bmeng.cn at gmail.com>

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