[PATCH v2] riscv: ax25: cache: Remove SPL_RISCV_MMODE config check

[Pragnesh Patel]

Hi Bin,

>-----Original Message-----
>From: Bin Meng <bmeng.cn at gmail.com>
>Sent: 14 March 2020 18:57
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Atish Patra
><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Paul
>Walmsley <paul.walmsley at sifive.com>; Rick Chen <rick at andestech.com>;
>Trevor Woerner <trevor at toganlabs.com>; Simon Glass <sjg at chromium.org>
>Subject: Re: [PATCH v2] riscv: ax25: cache: Remove SPL_RISCV_MMODE config
>check
>
>Hi Pragnesh,
>
>On Sat, Mar 14, 2020 at 6:48 PM Pragnesh Patel <pragnesh.patel at sifive.com>
>wrote:
>>
>> CONFIG_IS_ENABLED(FOO) will check FOO config option for U-boot,
>
>Looks you forgot to update ...

Ooops, Will send v2 again, please ignore this patch.

>
>> SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
>> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
>> ---
>>  arch/riscv/cpu/ax25/cache.c | 16 ++++++++--------
>>  1 file changed, 8 insertions(+), 8 deletions(-)
>>
>
>Regards,
>Bin